Catapult C Synthesis
Full-Chip High-Level Synthesis
Catapult C Synthesis is a high-level synthesis tool for ASIC and FPGA hardware designers who need to deliver optimal implementations with aggressive time-to-market requirements.implementations with aggressive time-to-market requirements.
Traditional hardware design methods that require hand-written RTL development and debugging are too time-consuming and error prone for today’s complex designs. Catapult C empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level. From these high-level descriptions, Catapult C generates production quality RTL.
With this approach, full hierarchical systems comprised of both control blocks and algorithmic units are implemented automatically, eliminating the typical coding errors and bugs introduced by manual flows. By speeding time to RTL and automating the generation of bug-free RTL, the Catapult C Synthesis tool significantly reduces the time to verified RTL.
Multimedia
Catapult C Primer
Technology OverviewThis short video gives an overview of Catapult C, explaining what it is, what it does and how design teams benefit from using it. View Video
Mobile Chip Design Using High-Level Synthesis
On-demand Web SeminarLearn how High-Level Synthesis has been used in mobile devices based on real-world experiences. View Video
More Videos, Demos, and Webinars
Customer Spotlight
STMicroelectronics
Within just a few years, the STMicroelectronics Imaging Division has gone from evaluating high-level synthesis to relying on Mentor’s high-level synthesis tool, Catapult® C, to create some of its most critical designs. STMicroelectronics
Features and Benefits
- Mixed datapath and control logic synthesis from both pure ANSI C++ and SystemC
- Multi-abstraction synthesis supports untimed, transaction-level and cycle-accurate modeling styles
- Full-chip synthesis capabilities including pipelined multi-block subsystems and SoC interconnects
- Power/Performance/Area exploration and optimization
- Push button generation of RTL verification infrastructure
- Advanced top-down and bottom-up hierarchical design management
- Fine-grain control for superior quality of results
- Built-in analysis tools including Gantt charts, critical path viewer, and cross-probing
- Silicon vendor certified synthesis libraries and integration with RTL synthesis for predictable backend timing closure
- ASIC and FPGA technology aware scheduling for high-performance hardware
- Broadest C++ language support including classes, templates and pointers
- Maximize IP and reuse potential with C++ object-oriented encapsulation
Datasheets
- Catapult C Synthesis (PDF, 2mb)
Toolbox
- TECHPUB: Boosting RTL Verification with High-Level Synthesis
- Technology Overview: High-Level Synthesis Primer
- On-demand Web Seminar: Hardware Designs Reuse Using C++ and High Level Synthesis
Contact Mentor Graphics
- Catapult C Synthesis Info Request or call toll free: 1-800-547-3000
From the Blogs
Take the High Road to Power-Optimized RTL
The latest edition of Chip Design Magazine features an insightful head-to-head discussion between Atrenta’s Kiran Vittal and Mentor’s Shawn McCloud. The topic: how to best achieve power-optimized RTL. Should…View Blog Post
The Best of Both Worlds
Today, Mentor Graphics announced that Catapult C now also synthesizes SystemC. This is significant news. Hardware designers can now adopt a high-level synthesis solution which will not limit them in any…View Blog Post
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