Catapult C Synthesis
Full-Chip C++ Synthesis
Catapult C Synthesis is a High Level Synthesis tool for ASIC and FPGA hardware designers of wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements.
New Features
New Features
Catapult C Synthesis unveiled breakthrough enhancements for control-logic synthesis and low-power design.
This short video provides an overview of the announcement and reviews the key features and benefits taking HLS to the next level.
Control-Logic and Low-Power Announcement HighlightsTechnology Overview
Multi-level Clock Gating
Multi-level Clock Gating
With its new multi-level clock gating optimization, Catapult C automates a major low-power design technique and delivers unrivalled power reduction.
This video explains how Catapult C’s low-power analysis and optimizations can help designers reduce power by up to 90%.
Multi-Level Clock Gating with Catapult C SynthesisTechnology Overview
Control-Logic Synthesis
Control-Logic Synthesis
Algorithmic synthesis delivers routinely proven benefits. But can control-logic provide comparable results?
This short video reviews the opportunities to improve productivity using the new Catapult C control-logic capabilities
Abstraction and Benefits with Control-Logic SynthesisTechnology Overview
Verification
Verification
When and how the interactions between control-logic blocks and algorithmic units should be verified?
This video presents Catapult C SCReplay, a genuinely novel and patent-pending verification solution which addresses this fundamental question.
The Catapult C Verification EdgeTechnology Overview
New in Catapult C Synthesis
- Support for control-logic synthesis from pure C++
- Decoupling Control Channel (DCC) technology allows easy interfacing between algorithmic blocks and control-logic blocks
- Accuracy for control units where you need it
- Abstraction for algorithmic blocks meaning faster verification, better results
- New patent-pending SCReplay for visibility and debug during verification
- Fully automated multi-level clock-gating providing near perfect clock gating
- Dynamic power management interfaces
- Reduces power consumption by an average 40%
Fastest Time to Verified RTL
Catapult C Synthesis reduces design time and verification effort. When writing pure C++, designers focus on the functional intent of their application. Timing and architectural information is abstracted away from the source description. With fewer details in the model, testbench development is also simplified.
Implementation of specific details are automatically added during the synthesis process, eliminating error-prone manual interventions and resulting in RTL designs correct by construction. Debug of the resulting RTL is in turn eliminated, further reducing the overall verification effort.
The Catapult C automated verification environment allows any RTL implementation of a C++ model to be verified using the original C++ testbench. This eliminates the need to write pin-level interfacing and bit-timed RTL environments to verify the RTL blocks created by Catapult before moving to system integration. Check out our demos and Automated Verification data sheet to see how C++ accelerates your design and verification efforts.
Unifying Control-Logic and Algorithmic Synthesis
Catapult C Synthesis is the first and only tool to synthesize full hierarchical systems comprised of both control blocks and algorithmic units from pure C++.
Its unique decoupling control channel (DCC) technology combined with a patent-pending verification flow form the key technological components of a unified flow for modeling, synthesizing, and verifying the complex mix of blocks commonly found in sophisticated applications. This lets users work within a standard and homogeneous environment for the creation of complete systems from a single source representation.
Bit-Accurate Data Types
Mentor Graphics provides the AC Data Types C++ class library. This stand-alone library facilitates the use of arbitrary length bit-accurate integer and fixed point types with improved semantic consistency and faster execution times while easily coexisting with SystemC data types for verification where needed.
Even if you are just modeling bit-accurate algorithms with no intent to synthesize them, and use nothing more than a C++ compiler, a free download of the AC Data Types will provide a high speed simulation solution with fast compile times for your bit-accurate algorithms.
Product Demos
Overview
Catapult C Synthesis - Overview
Product DemoSee how to create, synthesize, and verify several RTL implementations from the same C++ source using Catapult C Synthesis. View Video
Control
Catapult C Synthesis - Control Logic Demo
Product DemoSee how Catapult enables the design and synthesis of mixed control and algorithm block system-level designs written in C++. View Video
Low Power
Catapult C Synthesis - Advanced Clock Gating Demo
Product DemoSee how clock-gating optimizations are applied to a design by Catapult, and how the physical power savings are measured using integrated dynamic power analysis flows. View Video
Synthesizing Pure ANSI C++
By using pure ANSI C++ as the design language, users can leverage many established design entry, validation and verification tools without being locked into a proprietary language or methodology.
Widely used, simple to write and, most importantly, easy to learn, C++ is the language of choice to express and synthesize complex system functionality.
Pure C++ allows for the most abstract source description. Low-level hardware details are not modeled, letting designers explore and find the optimal architecture for given performance/area/power requirements. Coupled with C++ object-oriented programming, the reuse potential of the designs is maximized and taken to levels unknown with RTL and pin-level SystemC methodologies.
As a result, designers can generate high-quality RTL with Catapult and pure C++, 10-100x faster than other methods.
Features and Benefits
- ANSI C++ language synthesis with SystemC verification
- Dramatically reduces verification time through through automatic SystemC transaction level model (TLM) and testbench generation, allowing RTL tests using an untimed C++ testbench
- Create optimal hardware designs 10-100x faster than hand-coded methodologies for both control-logic and algorithmic blocks
- Significantly reduce dynamic power consumption, driven by advanced optimizations such as multi-level clock gating
- Incremental refinement methodology enables maximum user control over implementation and latency/area/throughput results
- Automatically synthesize interfaces to external hardware
- Production-proven: Over 200 ASIC tapeouts and hundreds of FPGA designs completed
Datasheets
- Catapult C Synthesis (PDF, 252kb)
- Captapult C Synthesis Automated Verification (PDF, 247kb)
Toolbox
- software eval: Evaluate Catapult C Synthesis
- Download: Algorithmic C Data Types
Contact Mentor Graphics
- Catapult C Synthesis Info Request or call toll free: 1-800-547-3000
Catapult C Library Builder
Catapult C Library Builder is a stand-alone tool that provides an easy and intuitive environment to generate and analyze design libraries for Catapult C Synthesis. Catapult C Library Builder
Low Power Solutions
Low Power designs give you the added boost you need to address power at every stage in the design flow – from ESL through functional verification all the way to physical implementation. Low Power Solutions