Customer Success
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Alcatel Space (ASIC and FPGA) "Using our traditional RTL flow, three blocks took approximately nine weeks to design. Once we were up to speed on Catapult C Synthesis, all three blocks were done in three weeks starting from the original untimed C source, representing an impressive 3x improvement. The most surprising outcome, however, was the resulting RTL design was not only equivalent to the hand-coded design but in some cases actually better (smaller and faster)." Alcatel Case Study Ericsson (ASIC) "Being able to achieve a 31 percent reduction in gate count, which correlates closely to silicon real estate and power consumption, speaks for itself. The cooperation between Mentor Graphics and Ericsson to develop a C-based tool that meets our requirements has been fantastic." Ericsson Case Study Nokia (FPGA) "The other flows we evaluated took weeks to meet — or failed to meet — our requirements. By comparison, the Catapult C-based flow exceeded our requirements in just two days! When we started evaluating Catapult C Synthesis, we quickly realized that we had found a winning solution. However, we had no conception that we’d move from using this tool in a beta site evaluation role to using it for mission-critical portions of our design so quickly." Nokia Case Study STMicroelectronics (ASIC) "Mentor Graphics' high level synthesis technology succeeded in providing desired area and speed results with a dramatic savings in time. Using Mentor’s Catapult C Synthesis, we were able to create a Reed-Solomon decoder with results equal to the best-published paper in a matter of days. We think that Catapult C Synthesis is a very valuable tool to speed up the path from untimed signal processing algorithms to silicon implementations." Henri Michel (customer since August 2001) |