Making the Right Architectural Decisions
Requires Flash Player.
In this session we will walk through a architectural design example to learn the value of doing system level analysis.
View On-demand Web Seminar
(Opens in New Window/External URL)
Details
Overview
Understanding what your system really needs to do before you build it is fundamental to success in developing today's complex systems. Architectural design is the task carried out by the system architects and SoC designers who need to partition, integrate and optimize complex systems with demanding power and performance constraints.
During the platform design process decisions need to be made related to hardware software partitioning, processor selection, interconnect and memory hierarchies, fabric infrastructures and caching strategies. These decisions have dramatic effects on the RTL that would be implemented for a system. Some level of detailed analysis of the effects of the decisions must be made to ensure the right architecture is implemented in RTL, by the time the RTL is developed it is often too late to change the fundamental architecture.
To address these issues system level design techniques are being used to create Transaction Level Models, TLMs, of the system that allow designers to make intelligent decisions between implementation choices before committing to the architectural choices in an RTL implementation.
In this session we will walk through a architectural design example to learn the value of doing system level analysis.
Some of the steps include:
- Creation of a system level transaction model
- Simulation of the TLM to approximate system processing and traffic
- Debug the platform to achieve confidence that it is appropriately modeling the system activity
- Analysis of the system to identify bottlenecks and potential tradeoffs in performance and power consumption
What You Will Learn
- Understand what an transaction level model is and how to create an initial platform
- Identify some of the tradeoffs that can be made at the transaction level
About the Presenter
Jon McDonald
Jon McDonald is Sr. Technical Marketing Engineer at Mentor Graphics. He received a BS in Electrical and Computer Engineering from Carnegie Mellon and an MS in Computer Science from Polytechnic University. He has been active in digital design, language based design and architectural modeling for over 15 years. Prior to joining Mentor Graphics Mr. McDonald held senior technical engineering positions with Summit Design, Viewlogic Systems and HHB Systems.
Who Should View
- System Engineers
- System Designers
- Project Leads
- Those who are responsible for the hardware tradeoffs within a system
Related Resources
Multimedia
How to Optimize System Power through Transaction Level Analysis and High Level Synthesis
During this webinar, we will describe a technique for adding power characteristics to transaction level models and how transaction level power analysis interacts with high level synthesis.…View On-demand Web Seminar
Mentor Graphics Low-Power Design Press Conference, DAC 2009
The Vista platform offers comprehensive architecture design and prototyping allows users to model, analyze and optimize power at the transaction level of abstraction.…View Technology Overview
Advanced SystemC Debug
Vista provides an advanced debug environment that was developed from the ground up to support SystemC. It handles both the software debug aspects, and the hardware debug aspects of traditional debug approaches,...…View Product Demo
Other Related Resources
Why You Should Optimize Power at the ESL
White Paper: The opportunities for optimizing a design for power are greatest at the architectural level of abstraction, where the design architecture is determined. The further a design moves downstream the less effective...…View White Paper
Realizing ESL with Scalable Transaction Level Models
White Paper: The OSCI TLM2 standard, scalable transaction-level models, and a methodology built around the Vista™ Model Builder technology overcome the three prevalent concerns about electronic system level design....…View White Paper
A Scalable Approach for TLM Across SystemC and SystemVerilog
White Paper: There are a number of compelling reasons that SystemC and SystemVerilog should co-exist in advanced verification environments. Hence, many attempts have been made to mix the two languages. The paper addresses...…View White Paper
