White Papers
Why You Should Optimize Power at the ESL
The opportunities for optimizing a design for power are greatest at the architectural level of abstraction, where the design architecture is determined. The further a design moves downstream the less effective optimization techniques become. Power optimization must begin at the electronic system level (ESL). Vista™ offers architectural analysis, exploration, and optimization of performance and power at the ESL. It features unique power modeling capabilities and a wide range of power analysis toolsets. Combining Vista with Catapult® creates a continuous power optimization path from the system level through synthesis to implementation. This flow and its benefits are described in this paper, along with a demonstration of using power policies to evaluate the effect of different architectural choices on power consumption.
Making the Case for HLS
Algorithms and architectures used in today’s new designs are so complex that traditional design practices are becoming inadequate. This paper gives an overview of the problems associated with the conventional design flow and how they can be addressed with a flow based on the simulation and synthesis of C (ANSI C, C++, or SystemC) representations. By automating an otherwise manual process, HLS eliminates the source of many design errors and accelerates a very long and iterative part of the development cycle.
Realizing ESL with Scalable Transaction Level Models
The OSCI TLM2 standard, scalable transaction-level models, and a methodology built around the Vista™ Model Builder technology overcome the three prevalent concerns about electronic system level design. This paper describes how these barriers to adoption have been addressed by the arrival of standard, scalable transaction-level models and the Model Builder methodology, and it presents an example of how to use Vista Model Builder for protocol aware timing simulation.
SystemC Modeling, Synthesis, and Verification in Catapult C
Catapult® C Synthesis added SystemC support for modeling, verification, and synthesis of complex ASICs at the system level. Both cycle-accurate and transaction-level (TLM) abstractions are supported, addressing SoC-specific needs such as bus interfaces and interconnects as well as connections with ESL flows. This Catapult flow promotes abstraction and design reuse. In this paper we will give an overview and a detailed example of SystemC support in Catapult.
Boosting RTL Verification with High-Level Synthesis
Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creating bug-free RTL designs. This can be realized today by automating the generation of RTL from exhaustively verified C++ models. If done correctly, high-level synthesis (HLS) can produce RTL that matches the high-level source specification and is free of the errors introduced by manual coding.
Advanced Clock Gating Techniques in Catapult C Synthesis
This whitepaper discusses one of the most important power optimization techniques used in Catapult C Synthesis – advanced clock gating optimization and analysis. Electronic System Level (ESL) design methodologies enable power consumption optimization opportunities unreachable for traditional RTL design methods. Learn how Catapult C Synthesis can help you deliver designs with minimum power dissipation using its several power optimization methods and power-aware architecture exploration capabilities.
A Scalable Approach for TLM Across SystemC and SystemVerilog
There are a number of compelling reasons that SystemC and SystemVerilog should co-exist in advanced verification environments. Hence, many attempts have been made to mix the two languages. The paper addresses the limitations of these current approaches, specifically in terms of scalability for multiple transactions types and dynamic allocation of data to be transferred across the language boundary. A general and scalable method for mixing SystemC and SystemVerilog data transactions and models will be presented, accompanied by working example code taken from real-life projects.
Hardware/Software Validation with a TLM Virtual System Prototype
With all the complexity associated with the hardware, the software is also crucial to the competitive success of these products. The application software often is the key differentiator for these consumer products, allowing the system company to reap substantial profit margins. Software is also key in the power and performance behavior of the hardware platform.
Using High-Level Synthesis for FPGA Development
Designing High Performance DSP Hardware using Catapult C Synthesis and the Altera Accelerated Libraries
Today's class of high-performance FPGAs such as the Altera Stratix III provide design engineers with a hardware platform that is capable of addressing the computational requirements needed to implement many of the next-generation wireless and video algorithms. Although these devices provide dedicated hardware to implement the basic building blocks of digital signal processing (DSP) algorithms such as multiply-accumulate (MAC), designers still must meet the challenges of rapidly taking an algorithm from concept to implementation in RTL.
Historically, the design flow consisted of modeling the algorithm functionality in a high-level language such as C++ and then hand-coding it in RTL. This manual method of RTL creation is not only time consuming and error prone, but often is highly sensitive to back-end routing delay problems. Catapult High-level C++ synthesis has historically been used to build ASIC hardware sub-systems found in extremely complex and compute intensive applications found in wireless, video and image processing. Combining Catapult's ASIC capabilities with Altera Accelerated Libraries provides designers with a rapid path from algorithms modeled in ANSI C++ to optimized RTL running in FPGA hardware. Furthermore, this design flow allows designers to directly target the FPGA DSP blocks from C++, easily solving back-end timing problems using high-level synthesis constraints.
Utilizing SystemC for Design and Verification
The number one reason for the use of SystemC is the significantly increased simulation performance at the TLM level over executable platforms modeled at the RT level using Verilog or VHDL. SystemC TL models are fast enough to serve as a software development platform allowing for early software development and for co-simulation of hardware and software. Both TL and functional models are fast enough for system level architectural modeling and analysis.
The second reason for SystemC use is functional verification. The same executable platform that is used to develop the software is often used for verification of the entire system. This verification occurs early on in a project and the TLM becomes a golden reference for the entire system. Because SystemC is C++, it has a number of inherent properties, such as classes, templates and inheritance, that lend themselves to verification. These capabilities are extended with the SystemC Verification Library (discussed later) making SystemC a powerful verification language as well as modeling language.
This exhaustive examination includes dozens of graphics, a glossary and code appendix.