Technical Publications
SystemC Modeling, Synthesis, and Verification in Catapult C
Catapult® C Synthesis added SystemC support for modeling, verification, and synthesis of complex ASICs at the system level. Both cycle-accurate and transaction-level (TLM) abstractions are supported, addressing SoC-specific needs such as bus interfaces and interconnects as well as connections with ESL flows. This Catapult flow promotes abstraction and design reuse. In this paper we will give an overview and a detailed example of SystemC support in Catapult.
Boosting RTL Verification with High-Level Synthesis
Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creating bug-free RTL designs. This can be realized today by automating the generation of RTL from exhaustively verified C++ models. If done correctly, high-level synthesis (HLS) can produce RTL that matches the high-level source specification and is free of the errors introduced by manual coding.
A Scalable Approach for TLM Across SystemC and SystemVerilog
There are a number of compelling reasons that SystemC and SystemVerilog should co-exist in advanced verification environments. Hence, many attempts have been made to mix the two languages. The paper addresses the limitations of these current approaches, specifically in terms of scalability for multiple transactions types and dynamic allocation of data to be transferred across the language boundary. A general and scalable method for mixing SystemC and SystemVerilog data transactions and models will be presented, accompanied by working example code taken from real-life projects.
Designing High Performance DSP Hardware using Catapult C Synthesis and the Altera Accelerated Libraries
Today's class of high-performance FPGAs such as the Altera Stratix III provide design engineers with a hardware platform that is capable of addressing the computational requirements needed to implement many of the next-generation wireless and video algorithms. Although these devices provide dedicated hardware to implement the basic building blocks of digital signal processing (DSP) algorithms such as multiply-accumulate (MAC), designers still must meet the challenges of rapidly taking an algorithm from concept to implementation in RTL.
Historically, the design flow consisted of modeling the algorithm functionality in a high-level language such as C++ and then hand-coding it in RTL. This manual method of RTL creation is not only time consuming and error prone, but often is highly sensitive to back-end routing delay problems. Catapult High-level C++ synthesis has historically been used to build ASIC hardware sub-systems found in extremely complex and compute intensive applications found in wireless, video and image processing. Combining Catapult's ASIC capabilities with Altera Accelerated Libraries provides designers with a rapid path from algorithms modeled in ANSI C++ to optimized RTL running in FPGA hardware. Furthermore, this design flow allows designers to directly target the FPGA DSP blocks from C++, easily solving back-end timing problems using high-level synthesis constraints.