Technical Publications

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Hardware/Software Validation with a TLM Virtual System Prototype

Posted in: ESL Design & Verification

With all the complexity associated with the hardware, the software is also crucial to the competitive success of these products. The application software often is the key differentiator for these consumer products, allowing the system company to reap substantial profit margins. Software is also key in the power and performance behavior of the hardware platform.

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Using High-Level Synthesis for FPGA Development

Posted in: High Level Synthesis
Next generation communication systems (Super 3G, WiMAX, etc.) will enable telecommunications carriers to deliver enhanced multimedia services at super-high-speeds. However, designing the hardware to support these systems has become more and more complicated. To implement these demands into an ASIC or FPGA, one must consider tradeoffs between design time, the size of the silicon implementation, and performance of the final system. Even more challenging, one must complete these larger, more complex designs faster to meet their tight time-tomarket windows. Thus, we have to introduce a new design methodology such as C-Based design.
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Designing High Performance DSP Hardware using Catapult C Synthesis and the Altera Accelerated Libraries

Posted in: High Level Synthesis

Today's class of high-performance FPGAs such as the Altera Stratix III provide design engineers with a hardware platform that is capable of addressing the computational requirements needed to implement many of the next-generation wireless and video algorithms. Although these devices provide dedicated hardware to implement the basic building blocks of digital signal processing (DSP) algorithms such as multiply-accumulate (MAC), designers still must meet the challenges of rapidly taking an algorithm from concept to implementation in RTL.

Historically, the design flow consisted of modeling the algorithm functionality in a high-level language such as C++ and then hand-coding it in RTL. This manual method of RTL creation is not only time consuming and error prone, but often is highly sensitive to back-end routing delay problems. Catapult High-level C++ synthesis has historically been used to build ASIC hardware sub-systems found in extremely complex and compute intensive applications found in wireless, video and image processing. Combining Catapult's ASIC capabilities with Altera Accelerated Libraries provides designers with a rapid path from algorithms modeled in ANSI C++ to optimized RTL running in FPGA hardware. Furthermore, this design flow allows designers to directly target the FPGA DSP blocks from C++, easily solving back-end timing problems using high-level synthesis constraints.

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Utilizing SystemC for Design and Verification

Posted in: ESL Design & Verification

The number one reason for the use of SystemC is the significantly increased simulation performance at the TLM level over executable platforms modeled at the RT level using Verilog or VHDL. SystemC TL models are fast enough to serve as a software development platform allowing for early software development and for co-simulation of hardware and software. Both TL and functional models are fast enough for system level architectural modeling and analysis.

The second reason for SystemC use is functional verification. The same executable platform that is used to develop the software is often used for verification of the entire system. This verification occurs early on in a project and the TLM becomes a golden reference for the entire system. Because SystemC is C++, it has a number of inherent properties, such as classes, templates and inheritance, that lend themselves to verification. These capabilities are extended with the SystemC Verification Library (discussed later) making SystemC a powerful verification language as well as modeling language.

This exhaustive examination includes dozens of graphics, a glossary and code appendix.

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Creating a Consistent Verification Environment from Algorithm to RTL

Posted in: High Level Synthesis
Hardware implementations of DSP designs typically start out as algorithms modeled in tools like Matlab(tm). Such tools provide a natural representation of the algorithm and an extensive collection of building blocks used to analyze algorithm performance, both quantitatively (S/N, BER, quantization errors, etc) and qualitatively (spectrum displays, processed image viewing, etc). They can also provide a quantitative analysis of possible fixed point implementations (rounding and saturation errors). However, as the design then moves to implementation in FPGA or ASIC hardware, the design must be recoded in a hardware description language (HDL) for synthesis. Verification of the recoded design using the original modeling tool becomes awkward and subject to human error as data files of input stimuli and responses are passed to and from the analysis tool. This paper outlines an alternate approach that uses C++ to code the initial algorithm, C++ software libraries of analysis functions for performance testing, an ESL synthesis tool to synthesize the C++ to HDL and a SystemC framework to verify the correct behavior of each synthesis transformation of the algorithm against the original C++. The result is a comprehensive DSP development environment with analysis and verification at any point from algorithm to FPGA/ASIC gate-level simulation.
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An ESL Methodology for Functional Verification between Untimed C++ and RTL using SystemC

Posted in: High Level Synthesis
Many RTL designs are developed from C++ algorithms that have been extensively tested using a C++ testbench. The C++ testbench often represents a huge engineering effort to provide as much coverage of the algorithm as possible. Once the algorithm has been synthesized to RTL, however, a new testbench is typically written instead of using the original C++ testbench. This creates a discontinuity between the verification performed on the sequential untimed C++ algorithm and the resulting RTL. This paper describes a methodology for performing Functional Verification between the original C++ and the RTL using a C++ testbench in a SystemC framework. Such a framework enables detecting errors in the RTL due to assumptions made during the synthesis of the C++ and avoids errors introduced in re-writing the testbench at the RTL level. Topics such as datatype conversion and transaction synchronization will be covered.
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Using a Catapult C-Based Flow to Speed Implementation and Increase Flexibility

Posted in: High Level Synthesis
This white paper first introduces conventional design flows and examines the associated problems that system architects and hardware designers face today. The paper next considers alternative approaches to hardware design based on the use of C and C++, including SystemC, Handel-C, and the synthesizable subset of pure untimed C++ used by Mentor's new Catapult? C Synthesis tool. The final sections in this white paper presents real world results outlining the increased productivity and implementation flexibility experienced by an R&D team using a Catapult C-based flow at the Nokia Research Center.
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Toshiba Creates Eigenvalue Decomposition Using Catapult C Synthesis

Posted in: High Level Synthesis

This report written by Toshiba Information Systems discusses the hardware implementation of "eigenvalue decomposition".  Eigenvalue decomposition is used in a wide range of applications for imaging, communication and audio such as image recognition using KL conversion, high-speed communication using MIMO antenna, and electric/sound wave arrival direction estimation using MUSIC method. It is expected that more than four antennas will be required in many cases for future MIMO communications and electric wave arrival direction estimation with MUSIC method applications. Here we were interested in verifying whether the method to obtain eigenvalues directly from the eigenvalue equation was reasonable or not. Therefore, we developed two effective algorithms in ANSI C++ to obtain eigenvalues and synthesized them with Catapult C Synthesis to compare the area versus the number of cycles at the algorithm level, respectively.

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