Alcatel Conquers the Next Frontier of Design Space Exploration using Catapult C Synthesis

Louis Baguena, ASIC/FPGA Design Manager at Alcatel Space states, "Using our traditional RTL flow, three blocks took approximately nine weeks to design. Once we were up to speed on Catapult C Synthesis, all three blocks were done in three weeks starting from the original untimed C++ source, representing an impressive 3X improvement".

This comprehensive case study shows how Alcatel addressed their satellite hardware design needs. Learn how Alcatel was able to leverage the same pure, untimed C++ already written by the system designer to create hardware using the Catapult C Synthesis tool. The Alcatel case study compares the traditional manual RTL flow with the new C based design flow using Catapult C Synthesis.