Catapult C Synthesis Addresses RTL Bottleneck in Ericsson's ASIC Design Flow
Contributor: ASIC/FPGA Design Manager at Alcatel Space: Louis Baguena
Format: PDF Document
Peter Nord, EDA and Methodology Coordination, Ericsson Mobile Platforms states, "Being able to achieve a 31 percent reduction in gate count, which correlates closely to silicon real estate and power consumption, speaks for itself. The cooperation between Mentor Graphics and Ericsson to develop a C-based tool that meets our requirements has been fantastic."
In this extensive case study you will see how Catapult C Synthesis addresses the classic RTL bottleneck faced by Ericsson's ASIC design teams. Ericsson discusses existing design challenges using traditional RTL design flows and barriers they face. The case study discusses how Ericsson was able to perform frequency exploration on a wider micro-architecture design space. Ericsson discusses how this new approach yielded designs which were 20-30% smaller than hand coded methods when running at the same design latency.
In this extensive case study you will see how Catapult C Synthesis addresses the classic RTL bottleneck faced by Ericsson's ASIC design teams. Ericsson discusses existing design challenges using traditional RTL design flows and barriers they face. The case study discusses how Ericsson was able to perform frequency exploration on a wider micro-architecture design space. Ericsson discusses how this new approach yielded designs which were 20-30% smaller than hand coded methods when running at the same design latency.