White Papers
Utilizing SystemC for Design and Verification
The number one reason for the use of SystemC is the significantly increased simulation performance at the TLM level over executable platforms modeled at the RT level using Verilog or VHDL. SystemC TL models are fast enough to serve as a software development platform allowing for early software development and for co-simulation of hardware and software. Both TL and functional models are fast enough for system level architectural modeling and analysis.
The second reason for SystemC use is functional verification. The same executable platform that is used to develop the software is often used for verification of the entire system. This verification occurs early on in a project and the TLM becomes a golden reference for the entire system. Because SystemC is C++, it has a number of inherent properties, such as classes, templates and inheritance, that lend themselves to verification. These capabilities are extended with the SystemC Verification Library (discussed later) making SystemC a powerful verification language as well as modeling language.
This exhaustive examination includes dozens of graphics, a glossary and code appendix.
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Why You Should Optimize Power at the ESL
The opportunities for optimizing a design for power are greatest at the architectural level of abstraction, where the design architecture is determined. The further a design moves downstream the less effective optimization techniques become. Power optimization must begin at the electronic system level (ESL). Vista™ offers architectural analysis, exploration, and optimization of performance and power at the ESL. It features unique power modeling capabilities and a wide range of power analysis toolsets. Combining Vista with Catapult® creates a continuous power optimization path from the system level through synthesis to implementation. This flow and its benefits are described in this paper, along with a demonstration of using power policies to evaluate the effect of different architectural choices on power consumption.
Realizing ESL with Scalable Transaction Level Models
The OSCI TLM2 standard, scalable transaction-level models, and a methodology built around the Vista™ Model Builder technology overcome the three prevalent concerns about electronic system level design. This paper describes how these barriers to adoption have been addressed by the arrival of standard, scalable transaction-level models and the Model Builder methodology, and it presents an example of how to use Vista Model Builder for protocol aware timing simulation.
A Scalable Approach for TLM Across SystemC and SystemVerilog
There are a number of compelling reasons that SystemC and SystemVerilog should co-exist in advanced verification environments. Hence, many attempts have been made to mix the two languages. The paper addresses the limitations of these current approaches, specifically in terms of scalability for multiple transactions types and dynamic allocation of data to be transferred across the language boundary. A general and scalable method for mixing SystemC and SystemVerilog data transactions and models will be presented, accompanied by working example code taken from real-life projects.
Hardware/Software Validation with a TLM Virtual System Prototype
With all the complexity associated with the hardware, the software is also crucial to the competitive success of these products. The application software often is the key differentiator for these consumer products, allowing the system company to reap substantial profit margins. Software is also key in the power and performance behavior of the hardware platform.