FPGA

Integrated FPGA Design Flow

Welcome to Mentor Graphics ASIC and FPGA HDL Design Creation and Synthesis solutions. With two decades of HDL-based development tool experience, Mentor Graphics delivers a range of product solutions from concept to implementation for requirements through project management and development.

DO-254 Solutions

Solutions for Requirements-Based FPGA Design Flows

Ensure the safety of in-flight hardware and meet FAA standards. Mentor delivers a best-practice methodology for requirements-based design to help you meet your DO-254 quality objectives while improving productivity. Learn more about Mentor's DO-254 solutions

Synthesis for DO-254 Design Assurance and other Safety-Critical Design Processes

techpub: RTCA/DO-254 (referred to as “DO-254”) is design assurance guidance for airborne electronic hardware. The Federal Aviation Administration (FAA), European Aviation Safety Agency (EASA), and other... View Techpub

Improving FPGA Prototyping with SystemVerilog

techpub: As ASIC designs have grown larger at a much faster pace than FPGA devices, often multiple FPGA devices must be used to prototype a single ASIC. The obstacle of using multiple devices is the task of connecting... View Techpub

FPGA Methodologies

Requirements Tracking

Track hardware implementation for requirement validation for safety critical projects in medical, transportation, aerospace and military, or any complex ASIC or FPGA design.

Design Creation

Mentor Graphics provides best in class tool supporting techniques and methodologies to accelerate the creation of thousands of lines of code to improve design productivity.

Design Reuse

Adopting new standards, tools, and methodologies will enable you to improve your design creation and reuse of legacy code, informal and formal IP.

Advanced FPGA Synthesis

Designers need a multi-vendor synthesis tool to keep pace with advances in technology. Precision RTL Plus is the industry's most comprehensive FPGA solution.

ASIC Prototyping

Ease the transition from ASIC to FPGA design by allowing the same HDL code and constraint syntax to be used.

IP-XACT

An XML Databook standard from the Spirit Consortium for a formalized approach to model IP.

SystemVerilog Design & Synthesis

Mentor Graphics enables designers to leverage the power of SystemVerilog for productive design creation, effective testbench development, and efficient synthesis.

Simulation

Delivering the highest simulation productivity possible with multi-language support and high-performance simulation engine.

Techpubs and Demos

FPGA Techpubs

Making the Case For an Integrated FPGA Design Flow

techpub: With the rate of ASIC-to-FPGA conversions continuing to escalate, choosing the right FPGA design tools can determine the course and competitiveness of a system house’s entire business. Design teams... View Techpub

Designing Multi-FPGA Prototypes That Act Like ASICs

techpub: FPGA prototyping has become indispensable for functional verification and early software integration of prospective ASIC designs. If the ASIC in question is large, it is often necessary to spread the functionality... View Techpub

Block-Based FPGA Design Flows Support Team Design and IP Re-use

techpub: Block-based design—a method of partitioning a complex FPGA design into natural sub-blocks—has become a necessity for many project teams. It not only streamlines the design and integration process... View Techpub

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RTL Reuse with HDL Designer

Product Demo

Do you use code from a previous design or an outsource group? Learn new techniques that can help you quickly understand code quality and estimate the effort required to reuse code. Let us show you how to... View Video

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News & Press