With increasing competitive pressures and shorter product life cycles, designers have less time to develop high performance and complex ASIC designs.
At the same time, the development cost of an ASIC is increasing rapidly, making it less feasible to use ASIC devices for many cost-sensitive applications without extensive testing and simulation. As FPGA devices have become larger and faster, verifying functionality of costly ASIC designs in FPGAs has become an effective and economical method of verification. However, some ASIC structures cannot be directly implemented in an FPGA efficiently.
Precision Synthesis helps ease the transition from ASIC to FPGA design by allowing the same HDL code and constraint syntax to be used. To obtain optimal performance, automatic conversions of ASIC design structures are utilized.
Automatic Gated Clock Conversion
Gated clock structures are used in ASIC to control the clock tree and power utilization. However, in an FPGA, gated clocks create huge clock delays and clock skew. To minimize these delays, gated clock structures are automatically converted to clock enable structures so that the dedicated clock lines can be utilized.
Conversion of DesignWare Instances
DesignWare components that have been instantiated in the ASIC design are also recognized and implemented in FPGA resources.
Support for ASIC Timing Constraints
The same Synopsys Design Constraint (SDC) format from the ASIC design can be used for the FPGA prototype. Precision Synthesis can import, use, and export SDC constraints.