There are currently no dates scheduled for this event

Overview

Very large and complex FPGAs introduced new opportunities for prototyping ASIC designs. With the increased capacity and performance that is now available in current FPGA offerings, ASIC systems can easily be verified and tested before costly decisions are made about the final design. The transition for ASIC design to FPGA design, however, is not always a push button affair. Considerations must be made for design content and the differences between the ASIC technology and the FPGA device. Choosing a design flow that will both accommodate the existing ASIC design and provide enough feedback and analysis capabilities in the prototyping process is instrumental in providing value from ASIC verification. This workshop will introduce:

1. ASIC prototyping with FPGAs
2. Design considerations that must be made in both the ASIC and the FPGA design to facilitate both devices
3. Design debugging and analysis
4. Performance enhancement techniques to provide the most realistic verification platform.

Time:

• 9:00 a.m. - 1:30 p.m.
• 4-hour workshop, 30% presentation / 70% hands-on

Agenda:

1. The need for ASIC prototyping with FPGAs
   1. Using FPGAs for verification
   2. Choosing the right FPGA
2. Making a smooth transition from ASIC design to FPGA design
   1. Selecting a design flow
   2. Considerations for technology specific cells
   3. Verifying the same ASIC code and constraint proves more value in the emulation process
3. Debugging and analysis of the prototype design
   1. Design analysis and cross-probing the FPGA and the RTL
   2. Making design changes efficient
4. Making decision in Synthesis to improve performance
   1. Timing analysis
   2. Resource management
   3. Performance enhancements for timing and area

Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot. Lunch and refreshments will be provided.