FPGA Design Assurance Workshop
There are currently no dates scheduled for this event.
Overview
A growing of number electronic systems make extensive use of FPGA designs. These same FPGAs are also growing in complexity. Many companies are failing to deliver these complex devices predictably, and with sufficient quality. Others are struggling to do so profitably. Both profitability and quality usually tie directly back to the design process itself. Most companies find that they do not have a structured, repeatable process that enables them to confidently deliver a high-quality, FPGA end-product.
FPGAs are an amazing invention. They enable designers to take an idea into silicon very quickly. The problem with complex FPGA devices is that haste, and ad-hoc process, do not always align with the goals of design assurance. A structured design process adopting the right tool for the right task can surely help you accomplishing these goals.
Seating is limited to maximize your learning experience, please submit your interest as soon as possible.
What You Will Learn
This hands-on, one-day workshop will cover the principles of a structured FPGA design process that is geared towards delivering both efficiency and a high-quality end product. The session discusses how modern design methods and tools support a structured design process. It also demonstrates this by taking an example design through pre-design activities (planning, conceptual design, requirements management), detailed design (RTL coding/checking, synthesis, P&R), verification (simulation, CDC checking, logical equivalency checking).
Whether you already have a good process and are open to incremental improvements, or you need an entire process overhaul, this workshop is for you.
Who Should Attend
Project managers, technical leads and engineers (both design and verification) who want to make improvements to their FPGA design flows.
Products Covered
Agenda
- 9:00-9:30 Registration
- 9:30 Introduction
- 9:40 Planning
- 9:45 Requirements Management
- 10:15 RTL Design
- 10:45 Coffee Break
- 11:00 RTL Lab
- 11:30 RTL Verification - CDC verification
- 12:45 Lunch Break
- 13:45 RTL Verification - CDC Labs
- 15:15 Synthesis
- 16:00 Coffee Break
- 16:15 Synthesis Labs
- 17:00 Gate-Level Verification
- 17:15 Equivalence-Checking Lab
- 17:45 Conclusion