FPGA Autumn Workshop
Are you designing FPGAs or are you planning to in the future?
Mentor Graphics and Gamma Sp. z.o.o. invite you to a free workshop training introducing you to current simulation and verification methodologies.
In this workshop, you will learn and experience the basic functionality of both ModelSim and Questa Core solutions “live”, and understand the different approaches to simulating and verifying your FPGA designs – you will understand the different levels of simulation and be able to assess the requirements for your designs.
The workshop will also guide you to understand one of the most common and successful method to automate verification by using assertions using live exercises.
All methods will be shown and trained using real examples that you will try out through hands-on exercises during the day on your own notebooks – after the workshop, you will be immediately able to start using what you learn!
Installation of the software and set up of the training files is provided prior to the seminar through Gamma Sp. z.o.o.
The training is free and will take place in Warsaw, Golden Plaza, Al. Jerozolimskie 123A Str (15th floor) on October 3 2013, 9am – 4pm. Registration is required.
We are looking forward to seeing you on the day!
About the Presenter
Neil holds a B.Eng in Electronic Engineering from Queen Mary College, University of London, and has over 20 years experience in ASIC and FPGA design. He worked initially for 8 years for several defence companies in the UK. From there, he went into applications engineering for first Actel and then Xilinx distributors where he supported many customers across the UK and Ireland. He then worked for 7 years for Saros Technology supporting numerous EDA vendors, including Mentor. Since joining Mentor Graphics in 2008, Neil has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects and giving technical presentations across Europe.
FPGA Verification with Assertions: Why Bother? A Painless and Easy Step-by-Step Approach to Adopting Assertions
This paper provides a practical, easy, step-by- step set of instructions on how to add assertions to your RTL design. By following the simple guidelines provided in this paper you will benefit by cutting...
ModelSim PE Simulation Download and Trial
Now is your opportunity for a risk free 21-day trial of the industry’s leading simulator with full mixed language support for VHDL, Verilog and SystemVerilog and a comprehensive debug environment...
Operating in a Mixed-language Environment Using HDL, C/C++, SystemC and SystemVerilog
C and C++ languages have an important role to play in ASIC design, and using these languages can significantly increase designer productivity. However, C and C++ cannot be used entirely alone; they must...