SystemVerilog for FPGA Designers

There are currently no dates scheduled for this event.

Overview

Modern FPGAs have seen tremendous advances in both performance and capacity. With these capabilities, designers are faced with the daunting task of verifying and validating that their design intent is represented in the finished product. SystemVerilog provides a comprehensive language that is a natural extension of Verilog, with the benefits of providing conciseness of expression, higher levels of abstraction, and unification of design and verification. Mentor Graphics' Precision® Synthesis provides the most complete SystemVerilog coverage for FPGA synthesis. This easy-to-use tool empowers designers to utilize sophisticated RTL and physical optimization algorithms to clearly express design intent.

Agenda

1. FPGA Designer Challenges
2. What is SystemVerilog
3. Benefits of SystemVerilog
4. SystemVerilog for Design & Synthesis
5. Achieving Optimal Results for SystemVerilog Designs

Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot. Lunch and refreshments will be provided.