Mentor.com :: FPGA Resources

On-demand Web Seminar:Safety-critical Applications and xtUML

Tue, 05 Feb 2013 18:39:01 GMT

Interest in adopting modeling practices is very high in domains requiring safety-critical design practices. In this presentation, the capabilities of BridgePoint and ReqTracer, two products from Mentor Graphics, are combined to implement a requirements-driven xtUML process that satisfies the requirements, verification, and code-quality needs of the safety-critical design community.

On-demand Web Seminar:Explore the True Potential of Your FPGA Design

Wed, 07 Nov 2012 18:22:27 GMT

In this seminar, you’ll discover how to leverage FPGA Precision Synthesis technology to find the true potential of your design.

Success Story:First time’s a charm for FPGA verification at Lockheed Martin Space Systems Company

Tue, 26 Jun 2012 16:59:58 GMT

Lockheed Martin uses SystemVerilog, OVM and Mentor Graphics tools for first-pass FPGA verification success

Multisession Event:Mentor Forum Finland

Wed, 20 Jun 2012 21:20:00 GMT

Mentor's Forum provides this opportunity, bringing together EDA industry experts, the EE design community, and solution providers – to collectively address the hottest issues, trends and products that affect the EDA industry.

Software Evaluation:ModelSim PE Simulation Download and Trial

Thu, 10 May 2012 07:00:00 GMT

Now is your opportunity for a risk free 21-day trial of the industry’s leading simulator with full mixed language support for VHDL, Verilog and SystemVerilog and a comprehensive debug environment include code coverage. ModelSim PE, act now – download and receive a 21-day license instantly.

Industry Article:Six Ways Synthesis Can Support Design Assurance in FPGAs

Wed, 18 Jan 2012 08:00:00 GMT

On-demand Web Seminar:ReqTracer + HDL Designer for Medical Applications

Wed, 21 Sep 2011 16:48:02 GMT

This webinar will present advanced chip design methods and practices that are now essential for any medical FPGA or ASIC design project.

On-demand Web Seminar:ReqTracer + HDL Designer for Mil/Aero Applications

Wed, 14 Sep 2011 17:56:46 GMT

This webinar will present advanced chip design methods and practices that are now essential for any mil/aero FPGA or ASIC design project.

On-demand Web Seminar:ReqTracer + HDL Designer

Wed, 07 Sep 2011 20:44:58 GMT

This webinar will present advanced chip design methods and practices that are now essential for any design project.

White Paper:Understanding electronic IP: common issues and how to find them

Mon, 22 Aug 2011 07:00:00 GMT

Using IP blocks in designs requiring DO-254 compliance is becoming more popular as a way to reduce costs and schedules. However, the use of IP comes with its own problems and pitfalls. A good methodology to better screen this IP before its usage can significantly reduce unexpected problems and lower risk, especially on safety critical designs. The most important soft IP screening technologies are automatic formal check and clock domain crossing analysis. This paper will provide a background explanation of IP, including: what types exist in the market; caveats to their usage; and suggestions to better analyze IP before it is used in a design, thus lowering risk and improving product safety. (Note: This paper does not address IP compliance issues. For more information on that topic, please refer to the DO-254 User Group paper "Use of Intellectual Property (IP) Cores in Airborne Electronic Hardware".