Mentor.com :: FPGA Resources

White Paper: Using Assertions to Satisfy Elemental Analysis

Thu, 03 Nov 2011 07:00:00 GMT

This paper discusses DO-254 and what it requires for verification (including advanced methods for DAL A/B designs), explains the original intent of Elemental Analysis, the way it is typically satisfied today with code coverage, introduces ABV, and proposes a method for using this technique to not only satisfy Elemental Analysis but also to support a systematic approach to satisfying a claim of Robustness testing.

On-demand Web Seminar:ReqTracer + HDL Designer for Medical Applications

Wed, 21 Sep 2011 16:48:02 GMT

This webinar will present advanced chip design methods and practices that are now essential for any medical FPGA or ASIC design project.

On-demand Web Seminar:ReqTracer + HDL Designer for Mil/Aero Applications

Wed, 14 Sep 2011 17:56:46 GMT

This webinar will present advanced chip design methods and practices that are now essential for any mil/aero FPGA or ASIC design project.

On-demand Web Seminar:ReqTracer + HDL Designer

Wed, 07 Sep 2011 20:44:58 GMT

This webinar will present advanced chip design methods and practices that are now essential for any design project.

White Paper:Using FPGA Synthesis to Protect Against Radiation Effects and Soft Errors

Thu, 01 Sep 2011 07:00:00 GMT

Mentor Graphics Precision® Hi-Rel automatically incorporates advanced mitigation circuitry during device-neutral RTL synthesis, thereby providing additional protection through the implementation flow itself. With support for SRAM, flash and antifuse architectures, this new technology can accelerate the development schedule, expand device options and reduce production cost.

White Paper:Understanding electronic IP: common issues and how to find them

Mon, 22 Aug 2011 07:00:00 GMT

Using IP blocks in designs requiring DO-254 compliance is becoming more popular as a way to reduce costs and schedules. However, the use of IP comes with its own problems and pitfalls. A good methodology to better screen this IP before its usage can significantly reduce unexpected problems and lower risk, especially on safety critical designs. The most important soft IP screening technologies are automatic formal check and clock domain crossing analysis. This paper will provide a background explanation of IP, including: what types exist in the market; caveats to their usage; and suggestions to better analyze IP before it is used in a design, thus lowering risk and improving product safety. (Note: This paper does not address IP compliance issues. For more information on that topic, please refer to the DO-254 User Group paper "Use of Intellectual Property (IP) Cores in Airborne Electronic Hardware".

Product Demo:ModelSim Simulation of Waveforms and Debug Demo for Beginners

Fri, 05 Aug 2011 07:00:00 GMT

This training provides an overview of Mentor Graphic's ModelSim® software. You will learn the basics about simulation and how to simulate with projects. You will learn how to work with multiple libraries and debug with the Dataflow window and view simulation waveforms in the Wave window. Finally, you will analyze simulation results with Waveform Compare. This training uses ModelSim v. 10.0.

After viewing the demo you will be able to:

Perform basic simulation and debug tasks
Simulate with projects
Work with multiple libraries
Debug with the Dataflow window
View simulation waveforms in the Wave window
nalyze simulation results with Waveform Compare

Skills Required

Background in digital logic design

Technology Overview:Introducing Precision RTL Plus + LeonardoSpectrum

Fri, 08 Jul 2011 18:21:00 GMT

Precision RTL Plus + LeonardoSpectrum provides a safe transition to state of the art synthesis Precision RTL Plus while preserving backward compatibility for legacy projects.

On-demand Web Seminar:How to Verify Rad-Tolerant Mitigation Circuitry

Thu, 30 Jun 2011 21:34:25 GMT

Once you’ve implemented rad-tolerant circuitry into your FPGA design, how do you verify that functionality is preserved? And how do you verify that the mitigation scheme actually works? Attend this session to learn about various methodologies and tool flows to implement rad-tolerant circuitry, automatically verify that design functionality is preserved, and verify the effectiveness of the mitigation schemes.

On-demand Web Seminar:Complementing Rad-Tolerant FPGAs with Synthesis-Based Mitigation

Thu, 30 Jun 2011 21:32:06 GMT

One of the most common approaches to radiation effects mitigation in FPGA design is simply opting for rad-tolerant silicon. However certain operating environments may entail further protection from single event effects such as single event transients (SETs). Attend this session to learn how synthesis-based radiation effects mitigation techniques complement the use of rad-tolerant devices to protect against both single event upsets (SEUs) and SETs.