FPGA Vendor Independence
It is critical for FPGA designers to retain the flexibility to retarget their designs to devices from different vendors. FPGA companies consistantly leapfrog each other in offering the biggest, fastest, or most power-efficient devices in the market. Designers are looking for methodologies that do not lock them into one FPGA vendor.
Mentor Graphics offers the industry’s most comprehensive and advanced vendor-independent solution for FPGA Design, with solutions spanning from system level design, through FPGA synthesis, to PCB layout. As part of this methodology, Mentor Graphics now offers a vendor independent IP platform within Precision Synthesis to facilitate the use of 3rd party IP for a variety of FPGA targets.
Precision RTL Plus is the latest addition to the Precision Synthesis family of products and builds on Precision RTL by delivering a vendor-independent solution for breakthrough productivity. Precision RTL Plus provides three industry-first capabilities for every designer, regardless of level of expertise, to reach timing closure faster, minimize the impact of design changes and make efficient use of FPGA architectural blocks. More
Intuitive logic synthesis environment with advanced optimization techniques, award-winning timing analysis, and advanced inferencing technology. Precision RTL enables vendor-independent design, accelerates time to market, eliminates design defects and delivers superior quality of results (QoR). More
All of the capabilities of Precision RTL and Precision RTL Plus with advanced physical synthesis environment offering interactive placement optimization capabilities for complex FPGA designs that enhances FPGA designer productivity and allows rapid timing convergence. More
Objective Device Selection
Project teams standardizing on vendor-independent tools can fully evaluate their device alternatives. Without being influenced by free vendor tools, designers can objectively compare the merits of one silicon device versus another and select the best FPGAs for their projects.
Reduce Development Costs
A single vendor-independent methodology allows designers to develop expertise on one flow regardless of the FPGA target. Engineers spend less time learning new tools and more time bring their product to market, thereby reducing development costs.
Efficient Design Re-Use
With a single flow for all FPGA devices, internal or 3rd party IP can be effectively re-used. When considering a device change, engineers benefit from a consistent design environment and need not be concerned with differences in language support, constraint formats, or synthesis optimizations between tools.