Manage Design Data and Flows
HDL Author increases the productivity of individual engineers while improving their ability to work as a team.
Advanced editors and HDL code visualization in graphical and tabular representations of the design speed the design creation and analysis of FPGA and ASIC designs. Time is money, but so is data, so HDL Author also helps designers, design teams and their companies save time by managing design data and design flows, thereby accelerating productivity.
Features & Benefits
- Efficiently create RTL designs using text, tables, and graphics
- Interactively manage design flow and all project data
- Facilitates management of ASIC/FPGA HDL design projects
- Enables an HDL design engineer to easily collaborate on design development with other teams of engineers
- Satisfies all design creation needs via textual, tabular and graphical design entry editors
- Designers can use a favorite HDL simulator and synthesis engine, creating an easier, more productive HDL design process
- Integrates other design tools easily with TCL, to run from within the HDL Author environment