HDL Designer combines deep analysis capabilities, advanced creation editors, and complete project and flow management, to deliver a powerful HDL design environment that increases the productivity of individual engineers and teams (local or remote) and enables a repeatable and predictable design process.
Features and Benefits
- Manages complex ASIC or FPGA designs in VHDL, Verilog and SystemVerilog
- Accelerates RTL Reuse
- Extensive design checking rules and rulesets
- Interactive HDL visualization and creation tools
- Automatic documentation features and reporting
- Intelligent debug and analysis
- Concurrent design entry and checking
Design and Reuse
- Quickly assess reused code quality and increase design understanding
- Efficiently create RTL designs using text, tables, and graphics
- Interactively manage design flow and all project data
- Rapidly produce documentation
- Accelerate IP repository population
- Manage and understand code relationships
- Accelerate language proficiency and results
- Summarize and quantify code characteristics
- Automate and simplify data management
- Design, measure and document for practical code reuse
HDL Designer assists engineers in analyzing, assessing, and visualizing complex RTL designs, providing code integrity analysis, connectivity completeness analysis, HDL code quality assessment, and design visualization.
Hand-in-hand with code analysis is code creation. HDL Designer provides engineers with a suite of advanced design editors to facilitate development: interface-based design spreadsheet editor (IBD) and block diagram, state-machine, truth table, flow chart and algorithmic state-machine editors. To complement these editors, HDL Designer includes an EMACS/vi-compatible, HDL-aware text editor.
In conjunction with design analysis and creation, design management is the third important task facing designers. Along with managing the design data, teams need to manage the project throughout the design flow.
HDL Designer tackles the design management problem by providing the designer with interfaces to other design tools within the flow; data and version management solutions.
HDL Designer also enables easy design and complete project documentation via HTML, OLE, print, and graphics export.
Lockheed Martin uses SystemVerilog, OVM and Mentor Graphics tools for first-pass FPGA verification success View Success Story
Aerospace manufacturer quickly achieves DO-254 compliance while improving verification quality and efficiency. View Success Story
The Olivetti team saved months of effort by managing their entire ASIC design process for their inkjet printer controllers using Mentor Graphics HDL Designer Series. View Success Story