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System & Block Diagram Editor

A customizable, hierarchical, mixed HDL, SOC Block Diagram design tool that is tightly integrated with leading synthesis, analysis, verification and design creation solutions for advanced FPGA and ASIC design. The perfect tool for capturing and rendering systems at any level of abstraction.


  • True mixed language structural editor: VHDL, Verilog, SystemVerilog, C/C++, PSL, SVA, SystemC
  • Creates optimal HDL code from direct graphical capture with integrated design checking and analysis.
  • Supports customizable corporate coding styles and promotes corporate reuse
  • Automatically reads any existing HDL code into a block diagram
  • Highly tuned place and route algorithms to create optimal diagram layout
  • Interactive integration with leading simulation tools: Questa, ModelSim, VCS, Incisive, NCSIM,
  • Tight integration with leading text editors (VI, Emacs, DesignPad)
  • Direct HTML creation for corporate design web site publication
  • Provides Design Report & Content Analysis


  • Dramatically reduces time for RTL / HDL entry
  • Enables fast reverse engineering of legacy code design
  • Improves IP based design processes
  • Significantly Improves HDL debug and analysis
  • Integrates tightly with all down-stream tools
  • Customizable to create your own flow
  • Automates design documentation processes
  • Promotes Reuse Methodology

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