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ReqTracer + HDL Designer for Medical Applications47:26On-demand Web Seminar: This webinar will present advanced chip design methods and practices that are now essential for any medical FPGA or ASIC design project. 47:26 Tags: DO-254, Requirements driven design, Requirements Tracing |
ReqTracer + HDL Designer for Mil/Aero Applications56:44On-demand Web Seminar: This webinar will present advanced chip design methods and practices that are now essential for any mil/aero FPGA or ASIC design project. 56:44 Tags: DO-254, Requirements driven design, Requirements Tracing |
ReqTracer + HDL Designer51:28On-demand Web Seminar: This webinar will present advanced chip design methods and practices that are now essential for any design project. 51:28 Tags: DO-254, Requirements driven design, Requirements Tracing |
How to Verify Rad-Tolerant Mitigation Circuitry24:30On-demand Web Seminar: Once you’ve implemented rad-tolerant circuitry into your FPGA design, how do you verify that functionality is preserved? And how do you verify that the mitigation scheme actually works? Attend this... 24:30 |
Complementing Rad-Tolerant FPGAs with Synthesis-Based Mitigation37:10On-demand Web Seminar: One of the most common approaches to radiation effects mitigation in FPGA design is simply opting for rad-tolerant silicon. However certain operating environments may entail further protection from single... 37:10 |
FPGA Design Assurance for DO-254 and Safety-Critical Applications33:00On-demand Web Seminar: Methodologies, tools, and flows for processes such as design synthesis for FPGAs must take DO-254 or design assurance requirements into consideration if the end products are slated for safety-critical applications.... 33:00 Tags: DO-254 |
Automated Triple Modular Redundancy: How and When to Use It36:22On-demand Web Seminar: Attend this webinar to learn how TMR during synthesis allows easy selection of the best TMR strategy for a target device without changing HDL code, while providing a formally verifiable mitigation solution... 36:22 |
Is Your Safe Design Safe Enough42:47On-demand Web Seminar: In this seminar, we explore the causes of soft errors such as SEUs and SETs and consider FPGA challenges when meeting safety-critical standards such as DO-254. 42:47 Tags: DO-254 |
Implementing Finite State Machines that Detect and Correct SEUs37:29On-demand Web Seminar: The prevention or detection of single event upsets (SEU) within critical control logic poses a challenge for airborne, space, or other high reliability applications. Manual methods are tedious and error-prone,... 37:29 |
Manage and Track Requirements in Your FPGA/ASIC Design Flow20:55On-demand Web Seminar: This webinar will cover the basic concepts of requirements tracing, the benefits of a requirements-driven design process, and how such an approach will assist you in meeting quality and standard compliance... 20:55 |
NASA Radiation Expert on Triple Modular Redundancy for FPGAs01:18:13On-demand Web Seminar: During this NASA presentation, common FPGA structures, their fault sensitivities, and device specific TMR strategies will be discussed and compared, including their mitigation effectiveness against single... 01:18:13 |
ModelSim Simulation of Waveforms and Debug Demo for Beginners48:36Product Demo: This training provides an overview of Mentor Graphic's ModelSim® software. You will learn the basics about simulation and how to simulate with projects. You will learn how to work with multiple libraries... 48:36 Tags: Debug, Simulation |