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Accelerating RTL Reuse



To meet the schedules and demands for complex ASIC and FPGA design projects, reusing HDL code as building blocks for new and next generation designs has become a common practice. Before committing pre-existing HDL blocks for reuse however, a design team often goes through a process to determine the code quality and builds an understanding of how the code will be incorporated into the new project.

What You Will Learn

  • This session will offer guidelines for code reuse and how to apply some practical approaches to accelerate the effort.

Who Should View

  • Engineers
  • Engineering Managers

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