Automated Triple Modular Redundancy: How and When to Use It
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Attend this webinar to learn how TMR during synthesis allows easy selection of the best TMR strategy for a target device without changing HDL code, while providing a formally verifiable mitigation solution for both single event upsets (SEUs) and single event transients (SETs).
Duration: 36:22
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Details
Overview
Attend this webinar to learn how TMR during synthesis allows easy selection of the best TMR strategy for a target device without changing HDL code, while providing a formally verifiable mitigation solution for both single event upsets (SEUs) and single event transients (SETs).
What You Will Learn
- The pros and cons of various mitigation strategies
- An automated and granular approach to TMR
- How and when to use automated TMR for specific architectures
About the Presenter
Roger Do
Roger Do is Synthesis Product Specialist at Mentor Graphics. He has over 16 years of FPGA experience, including previous roles in corporate and field applications and product marketing with Texas Instruments, Lucent Technologies, and Lattice Semiconductor. Roger holds a B.S. in Electrical Engineering from Texas A&M University.
Who Should View
- FPGA Designers of high reliability or aerospace applications
- Design Managers
- Program Managers
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