Automated Design Checking to Ensure Consistent RTL Quality
On-demand Web Seminar
Abstract
Design teams often have specific coding guidelines to ensure a level of consistency that needs to be enforced because RTL coding style and quality can vary greatly amongst engineers and can become both a design creation and a design reuse challenge. ASIC and FPGA designs contain a large volume of design IP code that comes from various sources inside and outside a company, the code needs to be quickly understood in terms of quality to keep a project on schedule.
Duration: 24:29
Details
Overview
Design teams often have specific coding guidelines to ensure a level of consistency that needs to be enforced because RTL coding style and quality can vary greatly amongst engineers and can become both a design creation and a design reuse challenge. ASIC and FPGA designs contain a large volume of design IP code that comes from various sources inside and outside a company, the code needs to be quickly understood in terms of quality to keep a project on schedule.
What You Will Learn
- In this session a practical approach to ensure RTL code quality consistency is demonstrated, along with coding recommendations for downstream synthesis and simulation success.
Who Should View
- Engineering Project Leads
- Engineering Managers
- Engineers
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