Fault Tolerant Finite State Machine (FSM) Design
On-demand Web Seminar
Abstract
This seminar will introduce a new FPGA synthesis capability for fault tolerant FSM design. FSM design traditionally proves to be a challenge for airborne or space applications. The prevention of single event upsets (SEU) must be addressed during FPGA design implementation. Existing methods of implementing safe FSM only includes limited SEU detection. New fault tolerant methods will not only include SEU detection but also error correction.
Duration: 18:30
Details
Overview
This webinar will introduce a new FPGA synthesis capability for fault tolerant FSM design.
FSM design traditionally proves to be a challenge for airborne or space applications. The prevention of single event upsets (SEU) must be addressed during FPGA design implementation. Existing methods of implementing safe FSM only includes limited SEU detection. New fault tolerant methods will not only include SEU detection but also error correction.
Who Should View
- Designers
- Design Managers
- Program Managers
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