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Formal Verification of Advanced FPGA Synthesis Optimizations



This webinar will introduce a new FPGA synthesis integrated design flow for logic equivalency checking formal verification.

Formal verification is a complimentary method of design verification to traditional RTL and gate-level functional verification. Formal verification has been used widely in ASIC design, but FPGA logic structures pose a more complicated problem. New design flow integrations between synthesis and formal verification tools can now support advanced FPGA synthesis optimizations and design assurance methods such as fault tolerant FSM encoding and TMR insertion.

Who Should View

  • Designers
  • Design Managers
  • Program Managers

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