Sign In
Forgot Password?
Sign In | | Create Account

Formal Verification of Advanced FPGA Synthesis Optimizations



This webinar will introduce a new FPGA synthesis integrated design flow for logic equivalency checking formal verification.

Formal verification is a complimentary method of design verification to traditional RTL and gate-level functional verification. Formal verification has been used widely in ASIC design, but FPGA logic structures pose a more complicated problem. New design flow integrations between synthesis and formal verification tools can now support advanced FPGA synthesis optimizations and design assurance methods such as fault tolerant FSM encoding and TMR insertion.

Who Should View

  • Designers
  • Design Managers
  • Program Managers

Related Resources


Explore the True Potential of Your FPGA Design

In this seminar, you’ll discover how to leverage FPGA Precision Synthesis technology to find the true potential of your design.…View On-demand Web Seminar

An Integrated Design Flow for FPGA/PCB Co-Design

By using advanced I/O optimization techniques and pin-aware FPGA physical synthesis, FPGA and board designers can meet design constraints in parallel and avoid unnecessary iterations. View this demonstration...…View Product Demo

Synthesis and DO-254 Considerations

Watch this presentation to learn about DO-254 principles and how to establish a requirements-based, high-quality design flow that supports the principles of DO-254 compliance.…View On-demand Web Seminar

Other Related Resources

Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools

White Paper: DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based...…View White Paper

Precision Synthesis: FPGA Design

Training Course: The Precision Synthesis: FPGA Design course will help you understand how to use Precision Synthesis to synthesize your design from HDL RTL to technology specific gate-level netlist. …View Training course

The Pivot Point for Design Flow Improvements

White Paper: Due to its placement at the junction between design creation and physical implementation, FPGA synthesis can provide significant leverage in meeting quality goals and reducing project cost and time. For...…View White Paper

Online Chat