Manage and Track Requirements in Your FPGA/ASIC Design Flow
On-demand Web Seminar
This webinar will cover the basic concepts of requirements tracing, the benefits of a requirements-driven design process, and how such an approach will assist you in meeting quality and standard compliance objectives, such as DO-254.
This webinar will cover the basic concepts of requirements tracing, the benefits of a requirements-driven design process, and how such an approach will assist you in meeting quality and standard compliance objectives, such as DO-254. Mentor Graphics ReqTracer is the powerful and flexible tool that will be presented and demonstrated in this webinar, enabling you to trace your system-level requirements all the way though your design implementation data and verification results.
Due to the increased complexity associated with the delivery of electronics and the increased use of distributed design teams, there exists a growing need to formalize and streamline requirements tracking. In complex electronic systems, requirements need to be traceable from enterprise level requirements databases through system design artifacts and down into the individual subsystem detailed design source files and verification results.
What You Will Learn
- Design requirements tracing and analysis capabilities from source to the design implementation and verification results
- Interfacing to key Mentor design tools such and Questa, HDL Designer and Certe Testbench Studio
- Links design and verification data into requirements-aware relationships and confirms these requirements have been implemented and fully tested
- Linking capabilities from diverse data in a variety of formats and bridging the traditional gap between requirements tools, design tools and test tools
About the Presenter
Walter has 19 years experience in ASIC/FPGA design and holds a MS in Electrical Engineering from Washington University in St. Louis. He worked for 6 years doing ASIC design at Tellabs Operations. From there, he went to work for Mentor Consulting where he consulted on various projects including time spent in Munich Germany and Helsinki Finland. For the last 5 years Walter has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects.
Who Should View
- Design Engineers
- Verification Engineers
- FPGA Designers
- Project Managers
- VP Engineering/Operations
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Other Related Resources
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