Meeting FPGA Project Deadlines using Incremental Design Flows

Overview

With 40% of FPGA projects running behind schedule, and with the primary reason being change in design specification, designers need a methodology that can incorporate design changes with minimal impact.

This session will discuss incremental compilation flows now available for FPGA synthesis, and in some cases place-and-route, that allow iterative changes to be localized only to the affected regions of the design, thereby shortening runtime and preserving quality-of-results.

Who Should View

• Engineering managers
• Project/team managers
• Engineers and designers