Implementing Finite State Machines that Detect and Correct SEUs
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The prevention or detection of single event upsets (SEU) within critical control logic poses a challenge for airborne, space, or other high reliability applications. Manual methods are tedious and error-prone, and traditional automated methods are often inadequate. This webinar discusses new automated methods to encoding finite state machines that detect and correct SEUs.
Duration: 37:29
Products: Precision Hi-Rel
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Details
Overview
The prevention or detection of single event upsets (SEU) within critical control logic poses a challenge for airborne, space, or other high reliability applications. Manual methods are tedious and error-prone, and traditional automated methods are often inadequate. This webinar discusses new automated methods to encoding finite state machines that detect and correct SEUs.
What You Will Learn
- Pros and cons of traditional "safe FSMs"
- How to encode FSMs to detect and recover from SEUs
- How to encode FSMs to correct from SEUs without interruption
About the Presenter
Roger Do
Roger Do is Synthesis Product Specialist at Mentor Graphics. He has over 16 years of FPGA experience, including previous roles in corporate and field applications and product marketing with Texas Instruments, Lucent Technologies, and Lattice Semiconductor. Roger holds a B.S. in Electrical Engineering from Texas A&M University.
Who Should View
- FPGA Designers of high reliability or aerospace applications
- Design Managers
- Program Managers
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