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Injecting Automation into Verification - Assertions

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Overview

What we will show in this webinar is how we can leverage Assertions, including the pre-defined, pre-tested OVL libraries, to automate the verification process further. What we will also show is the way in which the Assertion Manager will create pre-configured checkers as well as how to debug the results of an assertion failing. As the monitoring of the Assertions is done fully automatically by the simulator this further reduces the load of the engineer during verification and regression.

What You Will Learn

  • How to leverage assertions (including the pre-defined, pre-tested OVL libraries)
  • How to debug the results of an assertion failing
  • How they can be implemented within your verification environment

About the Presenter

Presenter Image Joe Rodriguez

Joe Rodriguez is a FPGA Market Development for Design Verification Technology (DVT) division at Mentor Graphics. Prior to this role Joe spent 2 years as Technical Marketing Manager for the Emulation Division (MED) at Mentor Graphics. Joe was also the Technical Marketing Manager in DVT at Mentor Graphics for 12 years. A result of this Joe has been involved in the definition and creation of many aspects of the Mentor Graphics verification solutions. Solutions like power aware simulation, debug and performance flows, including US patents for simulation event reduction.

Prior to Mentor Graphics, Joe spent 5 years as a field application engineer for Quickturn Design Systems successfully deploying many large FGPA based emulation projects. Joe also spent 6 years at Logic Automation as a Modeling Engineer and Support Manager. Joe has 7 years experience as a diagnostic engineer at Floating Point System and holds a Bachelor of Science in electrical engineering.

Who Should View

  • Design Engineers
  • Verification Engineers
  • Quality Engineers
  • Managers

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