NASA Radiation Expert on Triple Modular Redundancy for FPGAs
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During this NASA presentation, common FPGA structures, their fault sensitivities, and device specific TMR strategies will be discussed and compared, including their mitigation effectiveness against single event upsets (SEUs) and single event transients (SETs)
Duration: 01:18:13
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Details
Overview
Complexity Management and Design Optimization Regarding a Variety of Triple Modular Redundancy Schemes through Automation.
Field Programmable Gate Arrays (FPGAs) operating in environments containing ionizing energies are susceptible to faults. System upsets can range from a minor event such as erroneous data to catastrophic disruption of operation. In order to decrease error cross sections and satisfy critical space-system requirements, a myriad of mitigation strategies have been developed and are specific per FPGA architecture. Triple Modular Redundancy (TMR) is a common yet simple mitigation scheme based on majority voters and is employed in most critical systems. The efficacy of TMR depends on voter placement, correction capability, and degree of redundancy. Due to the difference in FPGA susceptibility characteristics, each family of devices may require different TMR schemes. Manual implementation becomes cumbersome and requires in-depth knowledge of FPGA ionizing fault characteristics.
In response, automated TMR insertion has been developed and is available through Mentor Graphics Precision Synthesis Tools. The uniqueness of this package is that various degrees of TMR are offered subsequently allowing the user to target a multitude of FPGAs.
During the presentation, common FPGA structures, their fault sensitivities, and device specific TMR strategies will be discussed and compared. This will be followed by Precision’s automated insertion process and an evaluation of the tool’s performance.
What You Will Learn
- Difference between FPGA structures and fault sensitivities
- An automated process to incorporate TMR during synthesis
- Evaluation of results of automated TMR insertion
About the Presenter
Melanie Berg
Chief Staff Electrical Engineer, MEI Technologies, NASA/GSFC Radiation Effects and Analysis Group
Melanie Berg received her MS degree in Electrical Engineering from the University of Pittsburgh in 1990. In 1988, during her graduate studies, Ms. Berg combined her expertise in chip placement and design methodology by creating optimized VHDL modules for Digital Systems of Pittsburgh PA. In 1990 Ms. Berg joined IBM's ASIC Advanced Logic Design Team in Poughkeepsie, NY. She has been part of several development teams responsible for high speed multi-million gate ASIC and complex FPGA implementations. Later in her career at Ball Aerospace, Ms. Berg was an FPGA designer and instructor for various space-flight projects. Ms. Berg is currently a member of IEEE and has joined the Radiation Effects and Analysis group at NASA Goddard Space Flight Center. She has published and presented several papers concerning such topics as Reliable Synchronous Design Methodology, Mitigation Strategies for Critical Circuitry, and Hardness Assurance for Space Flight Projects. Ms. Berg is presently investigating radiation effects and applicable mitigation strategies for the potential insertion of Field Programmable Gate Arrays (FPGAs) and ASICS into critical space flight projects.
Who Should View
- FPGA Designers of high reliability or aerospace applications
- Design Managers
- Program Managers
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