Triple Mode Redundancy (TMR) in Synthesis
On-demand Web Seminar
Abstract
This webinar will introduce a new FPGA synthesis capability for inserting TMR design structures during synthesis. The prevention of single event upsets (SEU) traditionally proves to be a challenge for airborne or space applications and must be addressed during FPGA design implementation. Common methods include manually inserting TMR in the RTL code which is tedious and error-prone, or using a TMR tool that will insert TMR structures after synthesis which limits user control and does not take design performance into consideration. Inserting TMR during synthesis enable designers with control over the insertion and performance optimization of the entire design with TMR.
Duration: 27:08
Details
Overview
This webinar will introduce a new FPGA synthesis capability for inserting TMR design structures during synthesis.
The prevention of single event upsets (SEU) traditionally proves to be a challenge for airborne or space applications and must be addressed during FPGA design implementation. Common methods include manually inserting TMR in the RTL code which is tedious and error-prone, or using a TMR tool that will insert TMR structures after synthesis which limits user control and does not take design performance into consideration. Inserting TMR during synthesis enable designers with control over the insertion and performance optimization of the entire design with TMR.
Who Should View
- Designers
- Design Managers
- Program Managers
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