In today’s high-end FPGAs, interconnect delay constitutes a significant part of the overall critical path delay. Traditional logic synthesis tools that estimate interconnect delay based on netlist structure can be far off target when predicting critical paths. Because of this, they produce netlists that result in sub-optimal post-place and route timing results. To address this problem, physical optimization techniques are needed that can optimize netlists based on accurate interconnect delay estimates and actual placement of the components. The paper describes advanced physical optimization techniques that improve performance of real-world designs by an average of 15%.