SystemVerilog is not a completely new hardware description language (HDL). With its rich set of extensions to the existing Verilog HDL, SystemVerilog is fully backward compliant with Verilog. Many of these extensions to Verilog make it easier to create accurate, synthesizable models of designs of any size. These extensions also make SystemVerilog easier to use and are truly beneficial to every engineer currently working with Verilog. This paper dispels the myth that only system designers need SystemVerilog, describing various enhancements of interest to all Verilog (and even many VHDL) users, regardless of the size or type of designs being modeled.