In many cases, design requirements refer to performance and area—the design needs to operate at a minimum frequency and naturally needs to fit into the selected device. Hence, designers or CAD managers looking to standardize on a synthesis flow tend to look for good out-of-the-box quality-of-results (QoR).

Often, to meet aggressive QoR goals, constraints need to be refined, optimizations must be enabled, or small portions of RTL may need to be re-coded—but without help from the tool it is difficult to identify when and where to make these changes. In other cases QoR goals may have been met but design changes are constantly being introduced, and new changes either degrade previous QoR results or runtime for each change delays project schedule. FPGA project managers must take into account these scenarios and consider how their synthesis flow addresses them.