This paper discusses how to automate RTL code design checking and how to synthesize the checked RTL code to produce correct by construction, fail-safe digital design techniques that implement a fault-tolerant design.

Addressing fail-safe design issues at the RTL code level is only the first of a two-step programmable logic design flow. Fail-safe and Single Event Upset (SEU) mitigation specific implementations at the RTL-to-gate synthesis process is also required before mapping a design into the device. Synthesis will allow trade-offs between fail-safe design methods such as safe finite-state-machine (FSM) implementation and redundancy versus performance and area optimization to predictably meet system design goals.