FPGA development teams use a variety of techniques to deal with radiation, such as rad-tolerant silicon, device- or board-level triplication, or HDL-level mitigation. While these are all viable, each technique comes with its own set of tradeoffs. One technology now available automatically incorporates mitigation circuitry during RTL synthesis, thereby addressing radiation protection through the tool flow. This paper first reviews some radiation basics, then examines traditional mitigation strategies commonly used today, and finally outlines how synthesis-based mitigation can offer an easier way to rad-tolerant FPGA design.