The Mentor Graphics Synthesis Partners Program brings together world-class silicon, software and IP vendors to benefit our mutual customers. Learn More
Mentor Graphics solutions deliver a best-practice methodology for requirements-based design to help you meet your DO-254 and quality objectives while improving the productivity of your flows and valuable resources. For early system-level verification of FPGA components, SystemVision provides a virtual lab for design and analysis of distributed mechatronic systems.
ASICs and FPGAs have progressed tremendously with complex FPGAs now requiring ASIC-like design methodologies. The expansion of HDLs from VHDL and Verilog to SystemVerilog has further fueled the necessity for sophisticated design and verification methodologies. Additionally, raising the abstraction level for design and synthesis from RTL to Electronic System Level (ESL) with languages such as C/C++ and SystemC has enabled engineers to understand the combined impact of the hardware and software architecture on system power, performance and functionality early in the design project. It is with these needs that we have created this ASIC/FPGA community to facilitate designers in communicating, collaborating, comparing, and occasionally commiserating, on ASIC and FPGA design.
We welcome all of your input