ASIC Prototyping with FPGAs
White Paper
ABSTRACT
Recently, there is a growing use of FPGAs to prototype ASICs as part of an ASIC verification methodology. With development costs for ASICs approaching $20M, avoiding a respin by prototyping with FPGAs is attractive alternative. This paper explorers the key issues designers should consider when developing and ASIC prototyping methodology.Related Resources
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