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FPGA Verification

FPGA devices have gone through radical changes in the last decade, becoming so complex they now resemble complete systems. As a result, they require advanced verification technology to improve FPGA debugging, deliver code coverage, and enhance verification throughput.

Mentor Graphics delivers the FPGA verification tools and expertise you need to get high-quality products out the door faster.

FPGA Verification

Providing Coverage

Code coverage is a critical step in FPGA verification:

  • Code coverage is a powerful debugging technique that can shorten the time required for verification by highlighting which parts of the design still needs testing.
  • Adding code coverage can improve FPGA lab productivity. The benefits are many but the main goal is to figure out how much of your code has been exercised so you don’t have to test the same code over and over again.
  • ModelSim’s code coverage is completely automated; just turn it on and use. There are no changes to your existing design or testbench.

Improving Debug with Assertions

  • Gain insight and visibility into your design by letting assertions notify you of an error so it can be fixed.
  • ModelSim provides a powerful library of checkers (OVL) letting you debug with assertions right away, without writing your own.
  • Assertions can also serve as documentation for your design, as comments are embedded into the code as you go.

Improving Throughput

  • Transaction Level Modeling (TLM) infrastructure is a fundamental step for improving test generation. Higher level tests improve throughput of scenario generation.
  • Higher level transactions enable debug throughput, leveraging high level transactions instead of decoding pin level activity
  • The Questa platform provides improved simulation throughput with Verification IP to drive protocol traffic, inject errors, debug at high level TLM activity and track functional coverage

 
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