Olivetti Eliminates Months of ASIC Design Effort
The ASIC design group at Olivetti I-Jet in Yverdon-les-Bains, Switzerland designs ASICs for their inkjet printer controllers. Projects like these, including prototyping the ASIC functionality on an FPGA before handing the design off to the ASIC vendor, must routinely be completed within a short six-to eight-month cycle. To manage the design process, the team standardized on Mentor Graphics® HDL Designer Series™.
“Our primary motivation in acquiring HDL Designer Series was to gain access to its design entry and visualization tools, which allow us to work a higher level than just VHDL or Verilog text entry.”
Alexandre Fotinos, EE Engineer, ASIC Designer, Olivetti I-Jet
The team of Messrs. Laurent Hausammann, Michel Pasche, and Alexandre Fotinos employ HDL Designer Series for every aspect of the project: from front-end design and controlling design iterations, through managing their IP portfolio and verifying the FPGA prototype, to finally preparing the design databases before shipment to the ASIC vendor.
The Design Task
Each six- to eight-month project involves the design of a million-gate ASIC for use in the company's inkjet printer controller cards. The team begins with the design specification, developing the custom blocks needed, combined with existing company IP to develop the RTL description of the ASIC. Once the high-level description has been completed, design verification can begin using simulation.
Prototyping the ASIC with FPGAs is crucial to the Olivetti's design verification process. The design is completed hierarchically, allowing the design to be easily partitioned into multiple FPGAs. Next, using an internally developed prototyping board populated with several FPGAs, processor, and memory blocks, the design code is verified in hardware. Once the hardware verification is completed, the entire design is reverified using the ASIC vendor's sign-off simulator.
HDL Designer Series in the Design Phase
The team utilizes HDL Designer Series to manage the entire design flow: from design entry and visualization to block synthesis and internally developed IP integration. The design visualization and entry tools within HDL Designer Series allow team members to work above the register-transfer level (RTL) when describing major sections of the design. This results in improved designer efficiency and accuracy.
Each engineer has specific responsibilities within the design effort but needs to work as a team to complete the entire project. The design management capabilities of HDL Designer Series allow the team members to share files and cooperate in developing the ASIC without impeding the efforts of the individual designer.
Each of the three team members has his own preferred design methodology and style. HDL Designer Series supports multiple entry methods of design description -- text, state machine diagram, flow chart, truth table, etc. -- allowing all engineers on the team to design how they want, but still cooperate efficiently on a single design.
Moreover, the design team makes use of company-developed IP blocks from previous designs. The HDL Designer Series design navigation and visualization tools enable a team member to quickly understand and integrate an IP block into the design. These same design management tools enable each team member to work on the specific blocks under his responsibility, so as to easily implement and verify each of the blocks while they still remain a part of the larger design.
Since the design will be verified in hardware, each block must be implemented in FPGA devices, which necessitates access to the FPGA vendors' tools. HDL Designer Series integrates these tools into a common environment, allowing each designer to easily create custom blocks targeted to the vendors' FPGA architecture.
More importantly, they can incorporate these sub-blocks within the design without leaving the HDL Designer Series user interface. Easy integration with the vendor's tools allows for pushbutton implementation and thus reduces the overall iteration times. Designers can focus on designing rather than supporting a script-driven flow environment.
HDL Designer Series in the Verification Phase
One of the challenges the team faces is that the design requirements typically remain in flux over most of the project's duration. At various stages in the design process, designers need to verify the functionality and performance of the design, starting at the block level and later for the entire design.
HDL Designer Series is also tightly integrated with ModelSim® from Mentor Graphics, the industry standard for logic simulation. This greatly facilitates simulator startup and control.
For debug, the design team makes extensive use of the crossprobing capabilities between ModelSim and HDL Designer Series, where simulation results are annotated in multiple design views, facilitating trace-back of signal faults. Cross-probing capability effectively saves the team days in design debug time.
HDL Designer Series and IP Management
Essential to the success of the Olivetti I-Jet ASIC team is the company's IP portfolio. Proper management of this portfolio has enabled the team to leverage past successes into future products. As standard blocks have been developed, they have been placed into the I-Jet IP library.
The visualization features within HDL Designer Series allow a designer to quickly understand and utilize these standard IP blocks within new ASIC designs. While many in the EDA industry speak of specifically designing IP for reuse, implementation is often hampered by the additional time and efforts required. With the design visualization and navigation features of HDL Designer Series, the I-Jet team has quickly developed a practical reuse methodology.
HDL Designer Series and Improved Teamwork
When all the advantages -- ease of front-end design, improved design debug, design flow management, and IP library management -- that HDL Designer Series brings to the I-Jet team's design flow are combined, it's clear that design efficiency is dramatically improved. The team estimates that HDL Designer Series has shaved ten percent out of the overall design time for an ASIC project. Given the six- to eight-month project cycle time, these savings translate into nearly three man months of saved time.
The powerful features of the HDL Designer Series environment effectively helps shorten the Olivetti I-Jet team's time-to-market, thus ultimately improving the division's profit levels.
“HDL Designer Series has saved us man months of effort across the entire design cycle.”
Laurent Hausammann, Senior EE Engineer, ASIC Designer, Olivetti I-Jet