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Testimonials - LeonardoSpectrum

Dillon Engineering

Solving the FPGA Timing Closure Challenge for High-Speed Designs (PDF)

Using the powerful RTL and physical synthesis capabilities of Precision Synthesis, the team at Dillon Engineering cut two weeks off of its design schedule, saved a speed grade (cost reduction up to $1,500 per device) and successfully achieved timing closure on a Xilinx Virtex II 3000 design.

CES Design Services

Precision Synthesis Helps CES Design Services Increase Timing Performance of a Complex FPGA Design (PDF)

"Precision RTL Synthesis, a simple synthesis run offers convincing area and timing estimates so that the number of place-and-route runs can be reduced considerably."

Johann Notbauer
Technical Director
CES Design Services

Siemens Industrial Solutions and Services

"Precision Synthesis delivers usability features that make it easier to synthesize designs which deliver better results. The intuitive interface allows synthesis operations to be completed with just a mouse click. More intelligence is built into each operation, making it easier to produce good results the first time a design goes through the tool. Combined with the fast synthesis run-times and interactive schematic viewing, we can increase our productivity for very large, high-speed designs. We look forward to running Precision Synthesis on our next project."

Alwin Hitzler
Senior Design Consultant
Siemens Industrial Solutions and Services Group


"With FPGA vendors providing larger and faster devices, we require a synthesis environment where our designers can easily take full advantage of these devices and one that can deliver on the performance promised by the vendors. Having a synthesis platform like Precision Synthesis, with its PreciseTime timing optimization and analysis engine that uses the industry standard SDC constraints format, will help Raytheon address this issue."

David Burson
Sr. Principal Electrical Engineer
Raytheon Electronic Systems

Mitsubishi Electric

"One of our biggest challenges is that we spend a considerable amount of time fixing timing issues in place and route, and we don't get enough information from synthesis tools to make good decisions. We feel that the advanced design analysis capabilities in the Precision Synthesis environment, with its PreciseTime feature, will help us correct timing issues in the front-end, save us time in place and route, and result in higher performance for our designs."

Hitoshi Matsumoto
Senior Design Engineer
Mitsubishi Electric Corporation
Communication Systems Development Center

Ericsson AB

"After P&R we missed the goal with slack of 1.0 - 1.5 ns. We tested several different timing setups and seeds but could meet the timing. A new physical placement run was done with a P&R and then we met the timing by 10ps. We only used [the] press button [automated Precision Physical flow], not manual placement or swapping of cells. The FPGA was nearly full. The main problem was bad placement of memories and multipliers inside the FPGA. After swapping the [MEM and MULT] blocks we started the automated flow in Precision Physical to solve the remaining timing violations in this FPGA. The improvement of timing was about 5-10%."

Lars-Göran Davidsson
Senior ASIC & FPGA Design Engineer
Ericsson AB, Radio Network Development (DRND) West

Andrew Corporation

"Great tool! Constraints are easy to set up and Precision Synthesis has drastically reduced our build time."

Dan Cohen
Senior Design Engineer
Power Amplifier Division


"The design analysis capability of Precision Synthesis helped streamline the design process with efficiency and accuracy…. The retiming, replication and re-synthesis features of Precision Synthesis greatly helped achieve timing closure on the entire design."

Vickie Wu
Senior Design Engineer
BroadLogic Network Technologies Inc.


"The powerful static timing analyzer, complex constraint editing capability, and the ease-of-use of Precision RTL helped us to quickly achieve timing, performance and resource utilization on the target device. This enabled us to meet our timing schedule and overall design goals."

Emmanuel Liegeon
Senior ASIC Designer
Alcatel Space

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