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Partners

The Mentor Graphics Synthesis Partners Program brings together world-class silicon, software and IP vendors to benefit our mutual customers. Becoming a partner enables vendors to gain access to Mentor Graphics synthesis software and library development tools for the purpose of flow testing, tool integration, library development, and supporting mutual customers. Partners will also be invited to collaborate with the Mentor Graphics sales organization when working with mutual customers.

Mentor Graphics FPGA Design Tools

  • Precision Synthesis
    Precision Synthesis forms the centerpiece of Mentor Graphics FPGA flow — the industry's most comprehensive vendor-independent synthesis tool for all FPGA applications including complex designs and ASIC prototyping. Precision Synthesis provides high quality of results, interactive design flows and award winning analysis which reduce design iterations, and enables faster, more predictable completion of designs.
  • HDL Designer Series
    HDL Designer delivers solutions optimizing the design creation, synthesis and verification processes of advanced ASIC and FPGA designs in a team environment.
  • FormalPro
    FormalPro is the Mentor Graphics high-capacity equivalence checking solution for regression testing of ASICs and FPGAs.
  • Seamless
    Co-verification environment that detects and isolates hardware/software interface errors for Platform FPGAs and systems for these devices.
  • ModelSim
    ModelSim PE is the industry-leading, Windows-based simulator for VHDL, Verilog, or mixed-language simulation environments.
  • I/O Designer
    I/O Designer provides bi-directional integration, data management and the ability to perform concurrent design of your FPGA and PCB.
  • Questa
    Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow.
  • Quesa Codelink
    Co-verification environment that detects and isolates hardware/software interface errors for Platform FPGAs and systems for these devices.
  • Nucleus
    The Nucleus RTOS is a proven embedded operating system that works out of the box and lets you focus your efforts on differentiating your products.

FPGA Design Tools

The MathWorks

Precision Synthesis now supports hardware description language (HDL) generated by MathWorks Simulink HDL Coder. The flow provides an easier path from Matlab/Simulink system models to FPGA implementation, ensuring an optimized netlist is generated. All mutual customers using Precision 2006a release or newer with Simulink HDL Coder can benefit from this flow, which will improve the productivity of FPGA design synthesis.

The MathWorks and Mentor Graphics have collaborated on this flow to assure interoperability. Simulink HDL Coder generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink models, Embedded MATLAB code, and Stateflow charts. For more information on Simulink HDL Coder:
http://www.mathworks.com/fpga-design/

Auspy

The integration between Auspy ACE Compiler and Precision Synthesis provide users the capability to produce high-performance prototyping platforms for complex ASIC designs.

Auspy Custom Emulator Compiler (ACE Compiler) maps designs in RTL or gate-level onto the custom-built or commercial prototyping platforms. The proprietary automatic partition algorithm produces high-quality solution with the minimum inter-FPGA connections and timing-correct high-speed prototypes. Get more information: http://www.auspy.com.

Temento Systems

The Precision Synthesis and DiaLite flow allows designers and users to use DiaLite Instrumentation tool to insert IPs instrumentation cores and to synthesize their designs in a fast and simple way. By delivering Temento Systems best-in-class debug tools with the automated generation of Precision Synthesis projects, users have access to the most advanced debug solution on the market.

DiaLite Instrumentation debug and verification tools offers best-in-class editions for “on chip” signal analysis and data collection “on silicon” to find behavioral malfunctions, plus the capability to visualize the HDL code executed when such an error occurs and finally check the most important specifications of the entire system using the latest Assertion Based Verification techniques. Get more information: http://www.temento.com/.

IP Providers

  • Vendor Independent IP
    Through the Precise-IP™ Partner Program, Mentor Graphics has partnered with leading IP vendors to offer a wide selection of cores validated for use with Precision Synthesis. Precise-IP™ incorporates a broad catalog of complex cores such as processors, interface controllers, and application-specific cores from a variety of industry-leading IP vendors.
  • Altera
  • Xilinx
 
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