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SystemVerilog Design & Synthesis

SystemVerilog is a powerful language that enables tremendous improvements in both advanced design and verification methodologies. However, to fully leverage the language, design and verification engineers need to become familiar with:

  • Object Oriented Programming Techniques
  • Methods for integrating existing VHDL and Verilog code
  • New constructs that enable coding at higher levels of abstraction

Adopting SystemVerilog as a language can prove to be a daunting task for many hardware designers unfamiliar with object-oriented language constructs. Mentor Graphics provides solutions that enable designers to leverage the power of SystemVerilog for productive design creation, effective testbench development, and efficient synthesis. These tools facilitate the understanding, creation and reuse of SystemVerilog code, providing a major productivity boost for both design and verification engineers working with SystemVerilog, AVM, and OVM-based environments.

Highlights

Challenges

  • Large number of design files and variety of HDL source code
  • Confusing file dependencies
  • Class extensions, inheritance and hard to follow relationships

Benefits

  • Effective Testbench Development
  • Productive Design Creation
  • Efficient FPGA Synthesis
 
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