White Papers - FPGA
Achieving Quality and Traceability in FPGA/ASIC Flows for DO-254 Aviation Projects
With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.
This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.
More White Papers
Understanding DO-254 and Solutions to Facilitate Compliance
RTCA/DO-254 (also known as DO-254 in the US or ED-80 in Europe) provides guidelines to facilitate requirements-based design of airborne electronic hardware. Now mandated by the US Federal Aviation Association (FAA) and many other aviation agencies and military programs, DO-254 establishes a standard to ensure that airborne custom micro-coded components (i.e., PLD, FPGA, and ASIC devices) perform their intended function under all foreseeable conditions.
First attempts to comply with DO-254 standards can be fraught with delays and unexpected costs. Project managers can minimize these difficulties if they understand what DO-254 compliance really entails, and modify their flows and toolsets to support it.
Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools
DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based Design for requirements analysis, design, automatic HDL code generation, and verification to produce airborne electronic hardware that adheres to DO-254. Model-Based Design for DO-254 combines automation tools from MathWorks and Mentor Graphics for design and verification to support a development process that goes from concept through implementation. This paper discusses this flow.
RTL and Synthesis Design Approach to Radiation-Harden and Fail-Safe Targeted Applications
This paper discusses how to automate RTL code design checking and how to synthesize the checked RTL code to produce correct by construction, fail-safe digital design techniques that implement a fault-tolerant design.
Addressing fail-safe design issues at the RTL code level is only the first of a two-step programmable logic design flow. Fail-safe and Single Event Upset (SEU) mitigation specific implementations at the RTL-to-gate synthesis process is also required before mapping a design into the device. Synthesis will allow trade-offs between fail-safe design methods such as safe finite-state-machine (FSM) implementation and redundancy versus performance and area optimization to predictably meet system design goals.
Planning SystemVerilog Adoption
Design demands have grown exponentially over time as fabrication capabilities and geometry sizes have improved drastically. The verification methodologies have not kept up and not changed a whole lot over at least four decades. Different attempts have been made at advancements but the solutions were proprietary or left to user’s imagination, at best. SystemVerilog amalgamates these previously attempted, disjoint technologies by extending a well known design language - Verilog. However, adopting new verification methods often seems unmanageable. This paper provides a new way for digital design and verification groups to easily adopt SystemVerilog. The paper opens with a historical review of how transaction-level modeling (TLM) has been used for design, followed by an explanation of how SystemVerilog can be useful for taking verification to the transaction level. We will look at how the Open Verification Methodology (OVM) addresses the vastness of the SystemVerilog language. The paper will finally propose a “next-generation” approach to design and verification management using SystemVerilog to improve verification methodologies by a couple of decades.
Demystifying DO-254
Interest in DO-254 first occurred in Europe and has since spread to the US commercial aircraft industry. If you are being asked about your company's DO-254 direction and compliance, but have been overwhelmed with information on the subject, then this article is for you. This article presents DO-254 for the novice, boiling down the standard, reducing it to its essential points so that you will be ready to respond with confidence, as well as understand its potential impact on your products or services.
Integrating HDL Designer Series and FormalPro Tools
When the decision is made to convert RTL code from one language to another, mistakes are unacceptable — the functionality of the new code must match that of the old. Any differences can lead to expensive and time consuming re-spins of the device. Unfortunately, mistakes are easy to introduce but difficult to find. This paper describes a methodology for automatically detecting all of the differences when converted RTL.
Scoring with HDL Designer
Have you ever wondered about the quality of code you are writing or that you plan to reuse from another engineer? Many teams have codified their RTL coding experiences into style guides providing rules and guidelines for creating designs. Unfortunately, these guides are rarely used or remembered. What if you could set up a tool that reflected your style guide? What if that tool could automatically provide you with a score representing the quality of your code? This paper presents how you can set up code quality assessment via rules and the scoring mechanism so your whole team can develop quality, re-usable code during your next project.
RTL Analysis and Creation using Spreadsheets
Today millions of users depend on spreadsheets, the most popular being Microsoft Excel, to organize, manage, analyze, model and generate numerical and text data. Spreadsheets are now making their way into hardware design. This paper covers the details of using the Interface Based Design (IBD) editor provided by Mentor Graphics HDL Designer Series(tm) to develop spreadsheets for hardware design.
Is SystemVerilog Only for System-Level Design
SystemVerilog is not a completely new hardware description language (HDL). With its rich set of extensions to the existing Verilog HDL, SystemVerilog is fully backward compliant with Verilog. Many of these extensions to Verilog make it easier to create accurate, synthesizable models of designs of any size. These extensions also make SystemVerilog easier to use and are truly beneficial to every engineer currently working with Verilog. This paper dispels the myth that only system designers need SystemVerilog, describing various enhancements of interest to all Verilog (and even many VHDL) users, regardless of the size or type of designs being modeled.