White Papers - FPGA

Updated for 2011, this paper provides background information and also goes into detail on FPGA synthesis challenges and solutions in high assurance design, including DO-254 environments.

Indeed, DO-254 is just one of many new or emerging standards among the safety- and mission-critical (or high assurance) design domains. Military, automotive, space, medical, nuclear, transportation, and industrial segments all have similar standards and/or concerns. The key objective of each of these standards is to ensure that the device produced will perform its intended function (as specified by requirements) under all foreseeable conditions. No specific methodologies or tools are inherently certified, compliant or qualified for these types of programs. However, many companies that are concerned about design assurance are reevaluating their design methods and tools – many of which described in this whitepaper – play an important role in overall program compliance, while also affecting productivity, schedule, budget, and design quality.

FPGA development teams use a variety of techniques to deal with radiation, such as rad-tolerant silicon, device- or board-level triplication, or HDL-level mitigation. While these are all viable, each technique comes with its own set of tradeoffs. One technology now available automatically incorporates mitigation circuitry during RTL synthesis, thereby addressing radiation protection through the tool flow. This paper first reviews some radiation basics, then examines traditional mitigation strategies commonly used today, and finally outlines how synthesis-based mitigation can offer an easier way to rad-tolerant FPGA design.

DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based Design for requirements analysis, design, automatic HDL code generation, and verification to produce airborne electronic hardware that adheres to DO-254. Model-Based Design for DO-254 combines automation tools from MathWorks and Mentor Graphics for design and verification to support a development process that goes from concept through implementation. This paper discusses this flow.

Due to its placement at the junction between design creation and physical implementation, FPGA synthesis can provide significant leverage in meeting quality goals and reducing project cost and time. For example, cross-probing tools offer debug capabilities that span the flow; other capabilities facilitate concurrent FPGA/PCB design. This paper explains how an FPGA synthesis tool, by integrating with advanced design and verification solutions, can help designers reach project goals more efficiently.

This paper discusses how to automate RTL code design checking and how to synthesize the checked RTL code to produce correct by construction, fail-safe digital design techniques that implement a fault-tolerant design.

Addressing fail-safe design issues at the RTL code level is only the first of a two-step programmable logic design flow. Fail-safe and Single Event Upset (SEU) mitigation specific implementations at the RTL-to-gate synthesis process is also required before mapping a design into the device. Synthesis will allow trade-offs between fail-safe design methods such as safe finite-state-machine (FSM) implementation and redundancy versus performance and area optimization to predictably meet system design goals.

Clock domain crossing (CDC) errors in FPGAs are elusive, and locating them often requires good detective work and smart design as well as an understanding of metastability and other physical behaviors. This white paper discusses the nature of CDC errors and presents a powerful solution that aids in their detection and removal. You can join the discussion forum on this topic at Mentor Communities.