White Papers - FPGA
Formal Verification for DO-254 (and Other Safety-Critical) Designs
Formal Verification (a.k.a., Formal Methods) is one of the few technologies mentioned by the RTCA/DO-254 document. It is listed as an example of an acceptable method for Appendix B "Advanced Verification" requirements for level A/B designs. However, many people (hardware applicants and certification authorities alike) do not have a good understanding of what Formal Verification is, how it works, and how it can or should be used within DO-254 programs. Using simple language, analogies and examples, this paper introduces Formal Verification in the context of its use for DO-254 and/or safety-critical programs, taking the ambiguity out of this powerful verification method.
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Understanding DO-254 and Solutions to Facilitate Compliance
RTCA/DO-254 (also known as DO-254 in the US or ED-80 in Europe) provides guidelines to facilitate requirements-based design of airborne electronic hardware. Now mandated by the US Federal Aviation Association (FAA) and many other aviation agencies and military programs, DO-254 establishes a standard to ensure that airborne custom micro-coded components (i.e., PLD, FPGA, and ASIC devices) perform their intended function under all foreseeable conditions.
First attempts to comply with DO-254 standards can be fraught with delays and unexpected costs. Project managers can minimize these difficulties if they understand what DO-254 compliance really entails, and modify their flows and toolsets to support it.
Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools
DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based Design for requirements analysis, design, automatic HDL code generation, and verification to produce airborne electronic hardware that adheres to DO-254. Model-Based Design for DO-254 combines automation tools from MathWorks and Mentor Graphics for design and verification to support a development process that goes from concept through implementation. This paper discusses this flow.
Code Coverage Explained: For DO-254 Projects
Level A/B designs governed by RTCA/DO-254 must have additional verification for added design assurance. DO-254 Appendix B specifies several methods by which this can be accomplished. Today, the most common method is "Elemental Analysis," which typically involves using code coverage to ensure that the verification activities exercise all the design code. The issue is that code coverage is not one thing, but rather an umbrella term that includes numerous code-oriented metrics. This paper explains each of those metrics, what is covered and what isn't, and how the Mentor Graphics functional verification tools can be used to easily generate these metrics during simulation.
The Use of Advanced Verification Methods to Address DO-254 Design Assurance
This paper covers a project that is using advanced functional verification methods to verify a RTCA DO-254/EUROCAE ED80 Level A/B design. These methods include Constrained Random Simulation, Design Intent Specification (designer-added assertions), the Total Coverage Model (Unified Coverage Database), and Formal Verification (formal model checking). The project is a real design currently being developed at Rockwell Collins.
Achieving Quality and Traceability in FPGA/ASIC Flows for DO-254 Aviation Projects
With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.
This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.
Optimizing FPGAs for High-Volume Applications
With the ASIC approach becoming more challenging and FPGA cost effectiveness improving, utilizing FPGAs is becoming more attractive for high-volume designs. An acceleration of this trend requires that FPGAs be precisely targeted to the requirements of high-volume designers.
This white paper examines specific factors impacting the optimization of an FPGA architecture in terms of the logic block, I/O support, external memory interfacing and configuration memory support. The paper concludes with an overview of the Lattice ECP/EC architecture.
Bluetooth Transceiver Design: A Top-Down Flow for Complex RF Mixed-Signal ICs
This paper describes the design challenges of BlueTraCTM, a low-cost, low-power radio transceiver. It details how a topdown methodology along with mixed-signal/mixed-mode techniques and behavioral modeling can be used to effectively address and solve the design challenges of this complex RF mixed-signal IC. The methodology leverages an out-of-the-box design flow from Mentor Graphics that includes Design Architect-IC for design entry and simulation control, Questa ADMS for single-kernel mixed-mode simulation, IC Station for schematic-driven physical layout, and Calibre for physical verification and extraction.