Technical Publications - FPGA
Making the Case For an Integrated FPGA Design Flow
With the rate of ASIC-to-FPGA conversions continuing to escalate, choosing the right FPGA design tools can determine the course and competitiveness of a system house’s entire business. Design teams can select proprietary solutions, commercial tools, and other alternatives. Some choices offer short-term cost advantages, others offer longer-term flexibility. This paper discusses the pros and cons of the diverse approaches available today.
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Enabling Model-Based Design for DO-254 Compliance with MathWorks and Mentor Graphics Tools
DO-254 compliance is becoming increasingly common on commercial and military aviation projects. Companies often struggle with the requirements and costs of DO-254 compliance. Engineers can use Model-Based Design for requirements analysis, design, automatic HDL code generation, and verification to produce airborne electronic hardware that adheres to DO-254. Model-Based Design for DO-254 combines automation tools from MathWorks and Mentor Graphics for design and verification to support a development process that goes from concept through implementation. This paper discusses this flow.
The Pivot Point for Design Flow Improvements
Due to its placement at the junction between design creation and physical implementation, FPGA synthesis can provide significant leverage in meeting quality goals and reducing project cost and time. For example, cross-probing tools offer debug capabilities that span the flow; other capabilities facilitate concurrent FPGA/PCB design. This paper explains how an FPGA synthesis tool, by integrating with advanced design and verification solutions, can help designers reach project goals more efficiently.
Keep Your FPGA Options Open With Vendor-Independent IP
This white paper introduces and advocates tools that allow designers to create vendor-independent FPGA configurations that can change as new technologies and customer demands emerge. Third-party IP elements such as DSP and processor cores play an important role in today’s FPGA design work, helping FPGA developers meet time-to-market and cost challenges in a competitive world. But relying on the proprietary IP that “came with the FPGA” is a recipe for limited choices in the future.
RTL and Synthesis Design Approach to Radiation-Harden and Fail-Safe Targeted Applications
This paper discusses how to automate RTL code design checking and how to synthesize the checked RTL code to produce correct by construction, fail-safe digital design techniques that implement a fault-tolerant design.
Addressing fail-safe design issues at the RTL code level is only the first of a two-step programmable logic design flow. Fail-safe and Single Event Upset (SEU) mitigation specific implementations at the RTL-to-gate synthesis process is also required before mapping a design into the device. Synthesis will allow trade-offs between fail-safe design methods such as safe finite-state-machine (FSM) implementation and redundancy versus performance and area optimization to predictably meet system design goals.
Diagnosing CDC Errors in FPGAs
Clock domain crossing (CDC) errors in FPGAs are elusive, and locating them often requires good detective work and smart design as well as an understanding of metastability and other physical behaviors. This white paper discusses the nature of CDC errors and presents a powerful solution that aids in their detection and removal. You can join the discussion forum on this topic at Mentor Communities.
Synthesis for DO-254 Design Assurance and other Safety-Critical Design Processes
This paper provides background information and also goes into detail on FPGA synthesis challenges and solutions in the DO-254 environment.
The goal of DO-254 is to ensure that airborne electronic hardware works reliably as specified, avoiding faulty operation and potential functional hazards. DO-254 hardware requirements define “design assurance” levels ranging from Catastrophic to No Effect. Methodologies, tools, and flows for processes such as design synthesis for FPGAs must take DO-254 requirements into consideration if the end products are slated for aerospace applications.
Designing Multi-FPGA Prototypes That Act Like ASICs
FPGA prototyping has become indispensable for functional verification and early software integration of prospective ASIC designs. If the ASIC in question is large, it is often necessary to spread the functionality across multiple FPGAs on a special prototype board. This white paper discusses the importance of choosing the right tools and methods to most efficiently partition ASIC functions into multiple FPGAs for development and evaluation purposes.
Block-Based FPGA Design Flows Support Team Design and IP Re-use
Block-based design—a method of partitioning a complex FPGA design into natural sub-blocks—has become a necessity for many project teams. It not only streamlines the design and integration process but also cuts down on implementation time when used with the right tool flows. The Mentor Graphics FPGA synthesis solution, Precision® RTL Plus, offers both a manual bottom-up methodology and a partition-based incremental flow for block-based design and implementation. It allows FPGA designers to cut down on run time while preserving quality-of-results (QoR) of unchanged design blocks
Improving FPGA Prototyping with SystemVerilog
As ASIC designs have grown larger at a much faster pace than FPGA devices, often multiple FPGA devices must be used to prototype a single ASIC. The obstacle of using multiple devices is the task of connecting all of the logical blocks of the ASIC design across multiple FPGA devices. However, methods for logically connecting the design blocks have proven to be manually intensive and error prone. With the introduction of SystemVerilog, an evolutionary RTL language, and advanced mixed language synthesis tools such as Mentor Graphics' Precision Synthesis, the procedure for connection has been simplified.