White Papers - FPGA
Raising the RTL Abstraction Level and Design Conciseness with SystemVerilog
With the advent of advanced HDLs that provide new and powerful language constructs, such as SystemVerilog, hardware modeling styles can now be enhanced both in terms of abstraction levels and overall efficiency. Developing concise, accurate designs entails learning how SystemVerilog features can be effectively used to design efficient and synthesizable models for both ASICs and FPGAs.
This paper will focus on the impact of new extensions and constructs in SystemVerilog on hardware designs and describe the usefulness and compatibility of these constructs vis-à-vis pure Verilog constructs
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Implementing SystemVerilog for FPGA Design
SystemVerilog has experienced broad adoption in verification, but not until recently did it receive much attention for its design constructs. The common explanation for this is that verification is the primary bottleneck in the design schedule; hence verification enhancements should logically be of the greatest interest. Recent studies show, however, that RTL implementation consumes nearly half of the design cycle, meaning that coding methodologies are far from perfect. SystemVerilog design constructs are intended to address the inefficiencies of conventional RTL design. This paper focuses on the set of language's constructs that raise the level of design abstraction to make RTL coding more intuitive, readable, and maintainable.