White Papers - FPGA

Safety-critical Applications and xtUML

On-demand Web Seminar 35:15

Safety-critical Applications and xtUML

Interest in adopting modeling practices is very high in domains requiring safety-critical design practices. In this presentation, the capabilities of BridgePoint and ReqTracer, two products from Mentor...

On-demand Web Seminar

Abstract

Safety-critical Applications and xtUML

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Explore the True Potential of Your FPGA Design

On-demand Web Seminar 19:27

Explore the True Potential of Your FPGA Design

In this seminar, you’ll discover how to leverage FPGA Precision Synthesis technology to find the true potential of your design.

On-demand Web Seminar

Abstract

Explore the True Potential of Your FPGA Design

In this seminar, you’ll discover how to leverage FPGA Precision Synthesis technology to find the true potential of your design.

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OVM Gets Connected

Blog Post

Abstract

OVM Gets Connected

OVM Bridges SystemVerilog and SystemC Languages When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog) and IEEE Std. 1666™ (SystemC) standards bridged the two languages to allow design and verification engineers to access UVM from SystemC or SystemVerilog to exploit native languages advantages. OVM users wondered if it was possible to support them…

TAGS: Multilanguage OVM, Multilanguage UVM, SystemC

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ReqTracer + HDL Designer for Medical Applications

On-demand Web Seminar 47:26

ReqTracer + HDL Designer for Medical Applications

This webinar will present advanced chip design methods and practices that are now essential for any medical FPGA or ASIC design project.

On-demand Web Seminar

DO-254, Requirements driven design, Requirements Tracing

Abstract

ReqTracer + HDL Designer for Medical Applications

This webinar will present advanced chip design methods and practices that are now essential for any medical FPGA or ASIC design project.

TAGS: DO-254, Requirements driven design, Requirements Tracing

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ReqTracer + HDL Designer for Mil/Aero Applications

On-demand Web Seminar 56:44

ReqTracer + HDL Designer for Mil/Aero Applications

This webinar will present advanced chip design methods and practices that are now essential for any mil/aero FPGA or ASIC design project.

On-demand Web Seminar

DO-254, Requirements driven design, Requirements Tracing

Abstract

ReqTracer + HDL Designer for Mil/Aero Applications

This webinar will present advanced chip design methods and practices that are now essential for any mil/aero FPGA or ASIC design project.

TAGS: DO-254, Requirements driven design, Requirements Tracing

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ReqTracer + HDL Designer

On-demand Web Seminar 51:28

ReqTracer + HDL Designer

This webinar will present advanced chip design methods and practices that are now essential for any design project.

On-demand Web Seminar

DO-254, Requirements driven design, Requirements Tracing

Abstract

ReqTracer + HDL Designer

This webinar will present advanced chip design methods and practices that are now essential for any design project.

TAGS: DO-254, Requirements driven design, Requirements Tracing

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FPGA Synthesis for High Assurance Design (Including...

White Paper

FPGA Synthesis for High Assurance Design (Including DO-254).

Updated for 2011, this paper provides background information and also goes into detail on FPGA synthesis challenges and solutions in high assurance design, including DO-254 environments.

White Paper

Abstract

FPGA Synthesis for High Assurance Design (Including DO-254).

Updated for 2011, this paper provides background information and also goes into detail on FPGA synthesis challenges and solutions in high assurance design, including DO-254 environments.

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Automated Triple Modular Redundancy: How and When...

On-demand Web Seminar 36:22

Automated Triple Modular Redundancy: How and When to Use It

Attend this webinar to learn how TMR during synthesis allows easy selection of the best TMR strategy for a target device without changing HDL code, while providing a formally verifiable mitigation solution...

On-demand Web Seminar

Abstract

Automated Triple Modular Redundancy: How and When to Use It

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Implementing Finite State Machines that Detect and...

On-demand Web Seminar 37:29

Implementing Finite State Machines that Detect and Correct SEUs

The prevention or detection of single event upsets (SEU) within critical control logic poses a challenge for airborne, space, or other high reliability applications. Manual methods are tedious and error-prone,...

On-demand Web Seminar

Abstract

Implementing Finite State Machines that Detect and Correct SEUs

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White Papers - FPGA

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